Embedded Systems - Hardware, Design and Implementation

Preface xv Contributors xvii 1 Low Power Multicore Processors for Embedded Systems 1 Fumio Arakawa 1.1 Multicore Chip with Highly Efficient Cores 1 1.2 SuperH RISC Engine Family (SH) Processor Cores 5 1.3 SH-X: A Highly Efficient CPU Core 9 1.4 SH-X FPU: A Highly Efficient FPU 20 1.5 SH-X2: Frequency and Efficiency Enhanced Core 33 1.6 SH-X3: Multicore Architecture Extension 34 1.7 SH-X4: ISA and Address Space Extension 47 2 Special-Purpose Hardware for Computational Biology 61 Siddharth Srinivasan 2.1 Molecular Dynamics Simulations on Graphics Processing Units 62 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations 72 2.3 Quantum MC Applications on Field-Programmable Gate Arrays 77 2.4 Conclusions and Future Directions 82 3 Embedded GPU Design 85 Byeong-Gyu Nam and Hoi-Jun Yoo 3.1 Introduction 85 3.2 System Architecture 86 3.3 Graphics Modules Design 88 3.4 System Power Management 95 3.5 Implementation Results 99 3.6 Conclusion 102 4 Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors 107 Tareq Hasan Khan and Khan Wahid 4.1 Introduction 107 4.2 The DVP Interface 108 4.3 The iBRIDGE-BB Architecture 109 4.4 Hardware Implementation 116 4.5 Conclusion 123 5 Embedded Computing Systems on FPGAs 127 Lesley Shannon 5.1 FPGA Architecture 128 5.2 FPGA Confi guration Technology 129 5.3 Software Support 133 5.4 Final Summary of Challenges and Opportunities for Embedded Computing Design on FPGAs 135 6 FPGA-Based Emulation Support for Design Space Exploration 139 Paolo Meloni, Simone Secchi, and Luigi Raffo 6.1 Introduction 139 6.2 State of the Art 140 6.3 A Tool for Energy-Aware FPGA-Based Emulation: The MADNESS Project Experience 144 6.4 Enabling FPGA-Based DSE: Runtime-Reconfi gurable Emulators 147 6.5 Use Cases 161 7 FPGA Coprocessing Solution for Real-Time Protein Identifi cation Using Tandem Mass Spectrometry 169 Daniel Coca, Istvan Bogdan, and Robert J. Beynon 7.1 Introduction 169 7.2 Protein Identifi cation by Sequence Database Searching Using MS/MS Data 171 7.3 Reconfi gurable Computing Platform 174 7.4 FPGA Implementation of the MS/MS Search Engine 176 7.5 Summary 180 8 Real-Time Confi gurable Phase-Coherent Pipelines 185 Robert L. Shuler, Jr., and David K. Rutishauser 8.1 Introduction and Purpose 185 8.2 History and Related Methods 188 8.3 Implementation Framework 191 8.4 Prototype Implementation 204 8.5 Assessment Compared with Related Methods 207 9 Low Overhead Radiation Hardening Techniques for Embedded Architectures 211 Sohan Purohit, Sai Rahul Chalamalasetti, and Martin Margala 9.1 Introduction 211 9.2 Recently Proposed SEU Tolerance Techniques 213 9.3 Radiation-Hardened Reconfi gurable Array with Instruction Rollback 223 9.4 Conclusion 234 10 Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip 239 Sudeep Pasricha and Yong Zou 10.1 Introduction 239 10.2 Related Work 240 10.3 Proposed 4NP-First Routing Scheme 242 10.4 Experiments 250 10.5 Conclusion 255 11 Interoperability in Electronic Systems 259 Andrew Leone 11.1 Interoperability 259 11.2 The Basis for Interoperability: The OSI Model 261 11.3 Hardware 263 11.4 Firmware 266 11.5 Partitioning the System 268 11.6 Examples of Interoperable Systems 270 12 Software Modeling Approaches for Presilicon System Performance Analysis 273 Kenneth J. Schultz and Frederic Risacher 12.1 Introduction 273 12.2 Methodologies 275 12.3 Results 283 12.4 Conclusion 288 13 Advanced Encryption Standard (AES) Implementation in Embedded Systems 291 Issam Hammad, Kamal El-Sankary, and Ezz El-Masry 13.1 Introduction 291 13.2 Finite Field 292 13.3 The AES 293 13.4 Hardware Implementations for AES 300 13.5 High-Speed AES Encryptor with Efficient Merging Techniques 306 13.6 Conclusion 315 14 Reconfi gurable Architecture for Cryptography over Binary Finite Fields 319 Samuel Antao, Ricardo Chaves, and Leonel Sousa 14.1 Introduction 319 14.2 Background 320 14.3 Reconfigurable Processor 333 14.4 Results 350 14.5 Conclusions 358 References 359 Index 363