High-Speed Clock Network Design
is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters.
Sprache
Verlagsort
Verlagsgruppe
Illustrationen
Dateigröße
ISBN-13
978-1-4757-3705-9 (9781475737059)
DOI
10.1007/978-1-4757-3705-9
Schweitzer Klassifikation
1 Introduction.- 2 Overview to Timing Constraints.- 3 Sequential Clocked Elements.- 4 Design Methodology for Domino Circuits.- 5 Clock Generation and De-Skewing.- 6 Microprocessor Clock Distribution Examples.- 7 Clock Network Simulation Methods.- 8 Low-Voltage Swing Clock Distribution.- 9 Routing Clock on Package.- 10 Balanced Clock Routing Algorithms.- 11 Clock Tree Design Flow in Asic.- Reference.
