Applied Reconfigurable Computing

Name: Applied Reconfigurable Computing | 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings
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13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings

Stephan Wong Antonio Carlos Beck Koen Bertels Luigi Carro(Herausgeber*in)

Springer (Verlag)

Erschienen am 30. März 2017

XX, 332 Seiten

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Beschreibung

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Inhalt

Intro
Preface
Organization
Invited Talks
Rethinking Memory System Design (and the Computing Platforms We Design Around It)
Acceleration Through Hardware Multithreading
Enabling Software Engineers to Program Heterogeneous, Reconfigurable SoCs
Contents
Adaptive Architectures
Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor
1 Introduction
2 Related Work
3 General Approach
3.1 When to Resize
3.2 How to Resize
4 Framework of Cache Resizing
4.1 Hardware Implementation
4.2 Resizing-LRU Replacement Algorithm
5 Evaluation
5.1 Experimental Platform Setup
5.2 Methodology
6 Results
6.1 The Impact of the Interval of Transition
6.2 About the Lasting Effect
7 Conclusions
References
LP-P2IP: A Low-Power Version of P2IP Architecture Using Partial Reconfiguration
1 Introduction
2 Energy Efficiency in FPGAs
2.1 Related Works
3 Modifications on P2IP
3.1 Configuration Mechanism
3.2 PR Applied on P2IP
4 Methodology
5 Results
5.1 Resource Analysis
5.2 Power Consumption Measurement
5.3 Reconfiguration Latency
6 Conclusions
References
NIM: An HMC-Based Machine for Neuron Computation
1 Introduction
2 NIM: A Neuron in Memory Approach
2.1 Computation: Minor Changes
3 Experimental Methodology and Evaluation of NIM
3.1 Methodology
3.2 Performance Results
3.3 Energy Consumption
4 Related Work
5 Conclusions
References
VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications
1 Introduction
2 Related Work
3 Implementation
3.1 Processing Elements
3.2 Memory Hierarchy
3.3 Platform
4 Experimental Setup
5 Evaluation Results
5.1 Resource Utilization
5.2 Image Processing Performance
6 Conclusion
References
Embedded Computing and Security
Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip
1 Introduction
2 Related Work
3 Hardware Sandboxing Concepts in SoCs
3.1 Sandboxing Concepts in Software
3.2 Structure of a Hardware Sandbox
4 Design Flow
5 Case Studies and Evaluation
6 Conclusion
References
Rapid Development of Gzip with MaxJ
1 Introduction
2 Background - High-Level Design
2.1 MaxJ Development Ecosystem
2.2 Altera OpenCL Compiler
3 Gzip
3.1 Gzip FPGA Implementation
4 MaxJ Implementation Advantages
5 Performance Evaluation
6 Productivity Discussion
7 Conclusion
References
On the Use of (Non-)Cryptographic Hashes on FPGAs
1 Introduction
2 Related Work
3 Use Cases and Attack Model
4 Hash Algorithms
5 Evaluation
5.1 Impact of Weaknesses in the Avalanche Effect
5.2 FPGA Implementation Results
6 Conclusion
References
An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications
Abstract
1 Introduction
2 The Fast Fourier Transform and the Radix-2 DIF Algorithm
3 Hardware Implementation of Radix-2 DIF FFT Algorithm
3.1 Implementation of Radix-2 SDF Pipelined FFT Architecture
3.2 Implementation of Twiddle Factor Multiplication in FFT
4 Experimental Results
5 Conclusion
Acknowledgments
References
Simulation and Synthesis
Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach
1 Introduction
2 Background
3 SPLC Design
3.1 Overview of the SPLC Architecture
3.2 Detailed Computation Layer
3.3 Detailed Configuration Layer
3.4 System Integration
4 SPLC Exploitation
4.1 Application Synthesis Targeting the SPLC Architecture
4.2 Timing Analysis
5 Experiments
5.1 SPLC Definition
5.2 Usage
6 Conclusion
References
FPGA Debugging with MATLAB Using a Rule-Based Inference System
Abstract
1 Introduction
2 Related Work
2.1 Debugging Using Logic Analyzers and HDL Simulators
2.2 Debugging Using Emulation Systems
2.3 Debugging Through Software
2.4 Hardware Co-simulation Based Debugging
2.5 Knowledge Based Automated Debugging System
3 Debugging by DSAS Approach with MATLAB Using Rule Based Inference System
3.1 Device Under Test (DUT)
3.2 Interfacing
3.3 Rule-Based Inference System
4 Results
5 Conclusions
References
Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs
1 Introduction
2 Fault Injection Methodology: How It Injects
3 Finding Fault Sensitive Locations: An Experimental Approach
4 RASP-FIT Tool
5 Methodology and Discussion
6 Conclusion
References
A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures
1 Introduction
2 Related Work
3 Proposed Approach
3.1 Basic CGRA Template
3.2 The Proposed Framework
4 Experimental Results
4.1 Computation Time Comparison for CGRA Vs. FPGA Implementations
4.2 Area and Power Results for CGRA vs. FPGA Implementations
5 Conclusion
References
Design Space Exploration
Parameter Sensitivity in Virtual FPGA Architectures
1 Introduction
2 Related Works
2.1 Virtual FPGA Architectures
2.2 Effects of Architectural Parameters on Area and Performance
3 The Generic V-FPGA Architecture
3.1 General Topology
3.2 Clustered Logic Cells
3.3 Routing Infrastructure
3.4 I/O Blocks
4 Area and Delay Models
5 Methodology of Parametric Design Space Exploration
6 Experimental Results and Analysis
6.1 The Effects of LUT Size Tuning on Area and Performance in Unclustered Architectures
6.2 The Effects of Combined Cluster Size N and LUT Size K Tuning on Area and Performance
7 Conclusions
References
Custom Framework for Run-Time Trading Strategies
1 Introduction
2 Background and Related Work
3 Framework for Reconfigurable Trading Strategies
4 Implementation Details
5 Library of Trading Strategies
6 Evaluation
7 Conclusion and Future Work
References
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation
1 Introduction
2 Multi-window SAD Matching Algorithm
3 High-level Synthesis Optimizations
4 Experimental Results
5 Conclusion
References
Architecture Reconfiguration as a Mechanism for Sustainable Performance of Embedded Systems in case of Variations in Available Power
1 Introduction
2 Related Works
3 MACROS Framework
4 Derivation of Power Consumption Estimation Model
5 PCE Model Application Analysis
6 Conclusion
References
Fault Tolerance
Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC
1 Introduction
2 Related Works
3 Proposed DCLS Technique in Zynq ARM-A9
3.1 Checker Module
3.2 Checkpoint Implementation
3.3 Rollback Implementation
4 Fault Injection Methodology
5 Experimental Results
5.1 Area and Performance Analysis
5.2 Fault Injection Analysis
6 Conclusion
References
Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs
Abstract
1 Introduction
2 TMR in Hardware Accelerators Generated by HLS
3 Fault Injection Method for Accumulated SEUs
4 Experimental Results
5 Conclusions
References
FPGA-Based Designs
FPGA Applications in Unmanned Aerial Vehicles - A Review
1 Introduction
2 Hardware of UAV and Commercial Platforms
3 High-Level Control
3.1 Stereo Vision
3.2 SLAM
3.3 Path Planning
3.4 Ego-Motion Estimation
3.5 Feature Extractor and Matcher
4 Low-Level Control
4.1 Stability Control
4.2 State Estimation
4.3 Interfacing with Sensors
4.4 Motor Control
5 Mission-Critical Tasks
5.1 Obstacle Avoidance
5.2 Object Recognition and Tracking
5.3 Communication System
6 Conclusion and Future Challenges
References
Genomic Data Clustering on FPGAs for Compression
1 Introduction
1.1 Genomic Data
2 Clustering
2.1 Parallel Clustering
3 Design Implementation
3.1 Software Setup
3.2 FPGA Architecture
3.3 Parallel Clustering
3.4 Hardware Setup
4 Tests and Results
5 Conclusions and Future Works
References
A Quantitative Analysis of the Memory Architecture of FPGA-SoCs
1 Introduction
2 Related Work
3 FPGA-SoCs
4 Architecture of Memory Engines
5 Experimental Design and Performance Analysis
5.1 Synthetic Benchmark
5.2 H.265/HEVC Trace-Based Benchmark
6 Conclusions
References
Neural Networks
Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms
1 Introduction
2 Background and Related Work
3 Architecture
4 Design Model Analysis
5 Optimisation Flow
6 Evaluation
7 Summary
References
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning
1 Introduction
1.1 Convolutional Deep Neural Network (CNN)
1.2 Problems of the Conventional CNNs
1.3 Proposed Method
1.4 Contributions of the Paper
1.5 Organization of the Paper
2 Convolutional Deep Neural Network (CNN)
2.1 Artificial Neural Network
2.2 VGG-11 CNN
3 Threshold Neuron Pruning
4 Circuit for the Fully Connected Layers After Threshold Neuron Pruning
5 Experimental Results
5.1 Threshold Neuron Pruning
5.2 FPGA Implementation
5.3 Comparison with the CPU and the GPU
6 Conclusion
References
Accuracy Evaluation of Long Short Term Memory Network Based Language Model with Fixed-Point Arithmetic
1 Introduction
2 LSTM in a Nutshell
3 Experimental Methodology
4 Influence of Shortened Bit-Width
5 Effect of Tanh Function Approximation
6 Mixed Bit-Widths
7 Conclusion
References
FPGA Implementation of a Short Read Mapping Accelerator
Abstract
1 Introduction
2 Related Works
2.1 FM-index
2.2 Recent FPGA Accelerators
3 Proposed Architecture
3.1 Exact Match Unit
3.2 Pre-calculated Data
3.3 Inexact Match Unit
3.4 Multi-core Version
4 Implementation and Experimental Results
4.1 Experimental Setup
4.2 Evaluating the Performance
4.3 Comparing the Results with Software
4.4 Comparing with Other Designs
5 Conclusion
References
Languages and Estimation Techniques
dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs
1 Introduction
2 Library Components
2.1 Reductions
2.2 Input and Output Blocks
2.3 Other Blocks
3 Benchmarking
4 Applications
5 Evaluation
6 Conclusion
References
A Machine Learning Methodology for Cache Recommendation
1 Introduction
2 Related Work
3 Proposed Methodology
4 Experimental Setup
5 Results and Discussion
6 Concluding Remarks and Future Work
References
ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality Test
1 Motivation
2 The Big Number Libraries
3 ArPALib Introduction
4 Tests of ArPALib as Software
5 A Case Study of ArPALib as Hardware
6 Conclusions
References
Author Index

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