The Verilog® Hardware Description Language

1 Verilog - A Tutorial Introduction.- 2 Behavioral Modeling.- 3 Concurrent Processes.- 4 Logic Level Modeling.- 5 Advanced Timing.- 6 Logic Synthesis.- 7 Behavioral Synthesis.- 8 User-Defined Primitives.- 9 Switch Level Modeling.- 10 Projects.- Appendix A Tutorial Questions and Discussion.- Structural Descriptions.- Testbench Modules.- Combinational Circuits Using always.- Sequential Circuits.- Hierarchical Descriptions.- Finite State Machine and Datapath.- Cycle-Accurate Descriptions.- Appendix B Lexical Conventions.- White Space and Comments.- Operators.- Numbers.- Strings.- Identifiers, System Names, and Keywords.- Appendix C Verilog Operators.- Table of Operators.- Operator Precedence.- Operator Truth Tables.- Expression Bit Lengths.- Appendix D Verilog Gate Types.- Logic Gates.- BUF and NOT Gates.- BUFIF and NOTIF Gates.- MOS Gates.- Bidirectional Gates.- CMOS Gates.- Pullup and Pulldown Gates.- Appendix E Registers, Memories, Integers, and Time.- Registers.- Memories.- Integers and Times.- Appendix F System Tasks and Functions.- Display and Write Tasks.- Continuous Monitoring.- Strobed Monitoring.- File Output.- Simulation Time.- Stop and Finish.- Random.- Reading Data From Disk Files.- Appendix G Formal Syntax Definition.- Tutorial Guide to Formal Syntax Specification.- Source Text.- Declarations.- Primitive Instances.- Module Instantiation.- UDP Declaration and Instantiation.- Behavioral Statements.- Specify Section.- Expressions.- General.