In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
Sprache
Verlagsort
Verlagsgruppe
Illustrationen
Dateigröße
ISBN-13
978-1-4419-6911-8 (9781441969118)
DOI
10.1007/978-1-4419-6911-8
Schweitzer Klassifikation
