VLSI-SoC: Design for Reliability, Security, and Low Power

Name: VLSI-SoC: Design for Reliability, Security, and Low Power | 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers
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23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers

Youngsoo Shin Chi Ying Tsui Jae-Joon Kim Kiyoung Choi Ricardo Reis(Herausgeber*in)

Springer (Verlag)

Erschienen am 12. September 2016

XIII, 223 Seiten

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978-3-319-46097-0 (ISBN)

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Inhalt

Intro
Preface
Organization
Contents
On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploration
1 Introduction
2 System-on-Chip Technology and Its Use in Space Exploration Avionics
3 The APEX-SoC Platform and Infrastructure
3.1 ARM-Centric Processing System
3.2 Data-Flow Infrastructure
3.3 Fault-Tolerance Features
3.4 Reliability Mode
4 Case-Study: APEX-SoC-Based Controller of the JPL CIRIS Spectrometer
4.1 The JPL CIRIS Spectrometer
4.2 CIRIS Data Processing
4.3 CIRIS Data Processing Integration into the APEX-SoC Infrastructure
5 Results
5.1 Implementation
5.2 Performance
5.3 Robustness Against Radiation
6 Conclusions and Future Work
References
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs
Abstract
1 Introduction
2 Structurally Synthesized BDD
3 Synthesis of SSBDDs
4 Fault Equivalence and Fault Dominance on the SSBDD Model
5 Fault Equivalence and Fault Dominance Fast Reasoning on the SSBDD Model
6 Lower and Higher Bounds for Fault Collapsing
7 Experimental Data
8 Conclusions
Acknowledgments
References
A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Images
Abstract
1 Introduction
2 Literature Survey
2.1 Sliding Window Based Pedestrian Detection
2.2 Real Time Pedestrian Detection
3 Overview of HOG
4 Hardware Architecture
4.1 Gradient Computation
4.2 Cell Histogram Generation
4.3 Block Histogram Normalization
4.4 SVM Classification
5 Results and Discussion
5.1 Experimental Setup
5.2 Accuracy Analysis
5.3 Throughput and Power Consumption Analysis
5.4 Choice of Parameters
6 Conclusion
Acknowledgments
References
Wearable ECG SoC for Wireless Body Area Networks: Implementation with Fuzzy Decision Making Chip
Abstract
1 Introduction
2 Prior Art
3 Wearable ECG System: With Decision Making
3.1 System Overview
3.2 ECG on Chip
3.3 Fuzzy Decision Making Chip: Concepts, Design and Implementation
4 Results and Discussion
4.1 ECG Acquisition
4.2 Fuzzy Decision Making
4.3 Performance Evaluation
5 Concluding Remarks
Acknowledgement
References
Delay Testing Based on Multiple Faulty Behaviors
1 Introduction
2 Functional Faults Caused by Distributed Additional Delay
3 Functional Delay Fault Models
3.1 Functional Delay Fault Model with Two Time Frames, FDF2
3.2 Functional Delay Fault Model with One Time Frame, FDF1
4 ATPG Methods Based on Incremental SAT Formulation
4.1 Application of Test Vectors
5 Experimental Results
6 Concluding Remarks
References
A Temperature-Aware Battery Cycle Life Model for Different Battery Chemistries
1 Introduction
2 Background and Motivations
2.1 Battery Aging Issues
2.2 Battery Aging Models
2.3 Motivations for the Work
3 Modeling Methodology
3.1 Model Definition
3.2 Analysis of the Mathematical Model
3.3 Extraction of Model Parameters
4 Model Validation
4.1 VRLA Batteries
4.2 Other Battery Chemistries
5 Extension of the Basic Model
5.1 Impact of the Temperature on Cycle Life
5.2 Impact of the Current on Cycle Life
5.3 Results
6 Conclusion
References
A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends
1 Introduction
2 ADC Architectures for CS Image Acquisition
3 SAR-Pipeline ADC Architecture for CS Measurements
4 Design Components
4.1 Stage 1 ADC and Residue Amplification
4.2 Stage 2 ADC
5 Analysis of Capacitor Mismatch
6 Simulation Results
7 Power Budget & Energy Efficiency
8 Comparison with Reported Works
9 Conclusion
References
Electromagnetic Transmission of Intellectual Property Data to Protect FPGA Designs
Abstract
1 Introduction
1.1 The Threat Model of IC and IP
1.2 Salware vs. Malware
2 EM Communication of IP Data
2.1 Principle
2.2 Ultra-Lightweight Digital BFSK Transmitter
3 Experimental Results
4 Second Version of the Ultra-Lightweight Digital EM Transmitter
5 Comparison with State of the Art Spy Circuitries Using a Side-Channel
6 Industrial Scenarios Using the Proposed IP Protection
7 Conclusion
Acknowledgment
References
JAIP-MP: A Four-Core Java Application Processor for Embedded Systems
Abstract
1 Introduction
1.1 Multi-core Java Processors
1.2 Potentials of Hardwired Virtual Machines
2 The Architecture of the JAIP Core
2.1 The Overview of JAIP Core
2.2 The Bytecode Execution Engine and the Stack Memory
2.3 Single-Core Preemptive Thread Management
2.4 The Memory Manager and Garbage Collector
2.5 Dynamic Symbol Resolution Unit and the I/O Subsystem
3 Multi-core Integration of JAIP
3.1 The Multi-core Thread Manager
3.2 The Data Coherence Controller Architecture
4 Experimental Results
4.1 Single-Core Multithread Performance Evaluation
4.2 Multi-core Multithread Performance Evaluation
4.3 Synchronization Overhead
5 Conclusions and Future Work
References
Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach
1 Introduction
2 Related Works
3 Background and Preliminaries
3.1 Definitions
3.2 Comparing Data Mining and Assertion Mining
4 Methodology
5 Assertion Mining
5.1 Mining of Interesting Behaviors
5.2 Pruning of Behaviours
5.3 Mining of Assertions
6 Assertion Qualification
6.1 Metrics
6.2 Assertion Ranking
7 Experimental Results
7.1 Assertion Qualification
8 Conclusions
References
Author Index

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