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This book proposes innovative circuit, architecture, and system solutions in deep-scaled CMOS and FinFET technologies, which address the challenges in maximizing the accuracy*speed/power of multi-GHz sample rate and bandwidth Analog-to-Digital Converters (ADC)s. A new holistic approach is introduced that first identifies the major error sources of a converter' building blocks, and quantitatively analyzes their impact on the overall performance, establishing the fundamental circuit-imposed accuracy - speed - power limits. The analysis extends to the architecture level, by introducing a mathematical framework to estimate and compare the accuracy - speed - power limits of several ADC architectures and variants. To gain system-level insight, time-interleaving is covered in detail, and a framework is also introduced to compare key metrics of interleaver architectures quantitatively. The impact of technology is also considered by adding process effects from several deep-scaled CMOS technologies.
The validity of the introduced analytical approach and the feasibility of the proposed concepts are demonstrated by four silicon prototype Integrated Circuits (IC)s, realized in ultra-deep-scaled CMOS and FinFET technologies.
Athanasios T. Ramkaj received the M.Sc. degree ( cum laude ) in electrical engineering (microelectronics) from TU Delft, Delft, The Netherlands, and the Ph.D. degree ( summa cum laude ) in electrical engineering from KU Leuven, Leuven, Belgium, in 2014 and 2021, respectively. Since June 2021, he has been with the Murmann Mixed-Signal Group, Stanford University, Stanford, CA USA, as a postdoctoral research fellow. In parallel, he is also a visiting researcher at Kilby Labs, Texas Instruments, Santa Clara, CA USA, investigating multi-GHz ultra-low jitter A/D solutions. From 2013 to 2014, he was an AMS research/design intern in the Central Research & Development Department of NXP Semiconductors, Eindhoven, The Netherlands, where he worked on GHz-range A/D converters for communication systems. In 2019, he was an AMS research/design intern with the High-Speed Data Converters group of Analog Devices Inc., Wilmington, MA USA, investigating highly integrated solutionsfor bandwidth extension of next generation RF A/D converters. His main research interests include high-speed/bandwidth high-resolution RF sampling A/D converters, high-speed analog/mixed-signal circuits for wireline and wireless systems, ultra-wideband receiver front ends, and ultra-low jitter clocking.
Marcel J. M. Pelgrom received his M.Sc. and Ph.D. degrees from Twente University, Enschede, The Netherlands. In 1979 he joined Philips Research Laboratories, wherehis research has covered topics as Charge Coupled Devices, MOS matching properties, analog-to-digital conversion, digital image correlation, and various analog building block techniques. He has headed several project teams and was as a team leader for high-speed analog-to-digital conversion products responsible for many Integrated Circuits. His IEEE JOURNAL OF SOLID-STATE CIRCUITS paper on MOS transistor mismatch is the most cited paper of this Journal. From 1996 till 2003 he was a department head for mixed-signal electronics research. In 2003 and 2014 he spent a sabbatical in Stanford University, Stanford, CA, USA, where he was appointed a consulting professor. Till 2013 he was a member of the technical staff of NXP Semiconductors, Eindhoven, The Netherlands. Next to the various activities concerning industry-academic relations, he was involved as a research fellow in research on substrate noise, variability and advanced conversion techniques. Presently, he is an independent consultant.
Michiel S. J. Steyaert received the M.Sc. degree in electrical and mechanical engineering and the Ph.D. degree in electronics from KU Leuven, Leuven, Belgium, in 1983 and 1987, respectively. From 1983 to 1986, he received the IWNOL Fellowship from the Belgian National Foundation for Industrial Research, which allowed him to work as a Research Assistant with the Laboratory ESAT, KU Leuven. In 1987, he was responsible for several industrial projects in the field of analog micropower circuits with the Laboratory ESAT as an IWONL Project Researcher. In 1988, he was a Visiting Assistant Professor with the University of California at Los Angeles, Los Angeles, CA, USA. He was appointed by the National Fund of Scientific Research, Belgium, as a Research Associate in 1989, as a Senior Research Associate in 1992, and as a Research Director with the Laboratory ESAT, KU Leuven, in 1996. Between 1989 and 1996, he was also a part-time Associate Professor. He was the Chair of the Electrical Engineering Department from 2005 until 2012. He is currently a Full Professor with KU Leuven. He was also the Dean of the Faculty of Engineering until 2020. He authored or co-authored over 500 papers in international journals or proceedings and co-authored over 24 books. His current research interests are in high performance and high-frequency analog integrated circuits for telecommunication systems and analog signalprocessing.
Filip Tavernier obtained the M.Sc. degree in electrical engineering and the Ph.D. degree in engineering science from KU Leuven, Leuven, Belgium, in 2005 and 2011, respectively. From 2011 to 2014, he was a Senior Fellow in the Microelectronics Group at the European Organisation for Nuclear Research (CERN), Geneva, Switzerland. From 2014 to 2015, he was a Postdoctoral Researcher with the Department of Electrical Engineering ESAT-MICAS of KU Leuven. From 2015 until 2020, he was an Assistant Professor, and since 2020, he is an Associate Professor at KU Leuven within the same department. His main research interests are analog and mixed-signal integrated circuits for high-performance data converters, DC-DC converters, optical receivers, and cryogenic circuits.
Prof. Tavernier is a Treasurer of the IEEE SSCS Benelux Chapter, an SSCS European Webinar Coordinator, a member of the Technical Program Committee of the European Solid State Circuits Conference (ESSCIRC) and the Custom Integrated Circuits Conference (CICC), and a member of the International Solid-State Circuits Conference (ISSCC) Student Research Preview Committee. He also serves as an Associate Editor for the IEEE SOLID-STATE CIRCUIT LETTERS.
Introduction.- Analog-to-Digital Conversion Fundamentals.- Architectural Considerations for High-Efficiency GHz-Range ADCs.- Ultrahigh-Speed High-Sensitivity Dynamic Comparator.- High-Speed Wide-Bandwidth Single-Channel SAR ADC.- High-Resolution Wide-Bandwidth Time-Interleaved RF ADC.- Ultra-Wideband Direct RF Receiver Analog Front End.- Conclusions, Contributions, and Future Work.
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