This book contains extended and revised versions of the best papers that were p- sented during the 16th edition of the IFIP/IEEE WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 16th conference was held at the Grand Hotel of Rhodes Island, Greece (October 13-15, 2008). Previous conferences have taken place in Edinburgh, Trondheim, V- couver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier, Darmstadt, Perth, Nice and Atlanta. VLSI-SoC 2008 was the 16th in a series of international conferences sponsored by IFIP TC 10 Working Group 10.5 and IEEE CEDA that explores the state of the art and the new developments in the field of VLSI systems and their designs. The purpose of the conference was to provide a forum to exchange ideas and to present industrial and research results in the fields of VLSI/ULSI systems, embedded systems and - croelectronic design and test.
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ISBN-13
978-3-642-12267-5 (9783642122675)
DOI
10.1007/978-3-642-12267-5
Schweitzer Klassifikation
Physical Design Issues in 3-D Integrated Technologies.- Universal Methodology to Handle Differential Pairs during Pin Assignment.- Analysis and Design of Charge Pumps for Telecommunication Applications.- Comparison of Two Autonomous AC-DC Converters for Piezoelectric Energy Scavenging Systems.- Trapping Biological Species in a Lab-on-Chip Microsystem: Micro Inductor Optimization Design and SU8 Process.- Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs.- Timed Coloured Petri Nets for Performance Evaluation of DSP Applications: The 3GPP LTE Case Study.- Real-Time Biologically-Inspired Image Exposure Correction.- A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters.- On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters.- Time Efficient Dual-Field Unit for Cryptography-Related Processing.- A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs.- A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication.- Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems.- Timing Error Detection and Correction by Time Dilation.
