Reversible Computation

Name: Reversible Computation | 9th International Conference, RC 2017, Kolkata, India, July 6-7, 2017, Proceedings
Brand: Springer
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9th International Conference, RC 2017, Kolkata, India, July 6-7, 2017, Proceedings

Iain Phillips Hafizur Rahaman(Herausgeber*in)

Springer (Verlag)

Erschienen am 26. Juni 2017

XII, 255 Seiten

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978-3-319-59936-6 (ISBN)

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Inhalt

Intro
Preface
Organization
Relating the Limits of Computational Reversibility to Emergence (Abstract of Invited Talk)
Contents
Invited Paper
Tools for Quantum and Reversible Circuit Compilation
1 Introduction
2 Data Dependency Analysis in Revs
3 An Example at Scale: SHA-256
4 Quantum Computing Software Architecture
5 Other Paradigms for Quantum and Reversible Synthesis
5.1 Using Dirty Ancillas
5.2 Repeat-Until-Success Circuits
5.3 Higher-Dimensional Alphabets
6 Conclusions
References
Foundations
Foundations of Generalized Reversible Computing
1 Introduction
2 Formulating Landauer's Principle
3 Reformulating Reversible Computing Theory
4 Examples of Conditioned Reversible Operations
5 Modeling Reversible Hardware
6 Comparison to Prior Work
7 Conclusion
References
Reversible Nondeterministic Finite Automata
1 Introduction
2 Preliminaries
3 Nondeterministic Reversible Finite Automata
3.1 Computational Power
3.2 On the Degree of Irreversibility
3.3 Closure Properties of REV-NFA Languages
4 Conclusions
References
Capacitive-Based Adiabatic Logic
1 Introduction
2 Buffer and Inverter Functions in CAL
3 Implementation of AND and OR Gates in CAL
4 Electromechanical Model of a Four-Terminal Variable Capacitor Element
4.1 Two-Terminal Parallel Plate Transducer
4.2 Four-Terminal Parallel Plate Transducer with Stopper
4.3 Energy Conversion and Losses
5 Conclusion
References
Implementing Reversible Object-Oriented Language Features on Reversible Machines
1 Introduction
2 Classes and Inheritance
3 Aliasing
4 Translation
4.1 Objects and Memory
4.2 Methods
4.3 Dynamic Dispatch
5 Conclusion
References
Reversible Circuit Synthesis
Designing Parity Preserving Reversible Circuits
1 Introduction and Motivation
2 Reversible Logic Synthesis
3 Theoretical Results
3.1 Direct Method of Converting Irreversible Specification to Parity-Preserving Reversible Specification
3.2 Algorithm and Its Complexity Analysis
4 Experimental Results
4.1 Comparison with State-of-the-Art
4.2 Tests for Boolean Functions with Large Variable Count
5 Conclusion and Future Work
References
REVS: A Tool for Space-Optimized Reversible Circuit Synthesis
1 Introduction
2 Reversible Circuits
3 Dependency Analysis
3.1 Mutable Data Dependency Graphs (MDDs)
3.2 Eager Cleanup Strategy
4 Boolean Expression Generation
4.1 Boolean Function Synthesis Benchmarks
4.2 Optimizations for Boolean Circuits
5 Conclusions
References
Towards VHDL-Based Design of Reversible Circuits
1 Introduction
2 Realizing VHDL Signals
3 Realizing VHDL Statements
3.1 Signal Assignment
3.2 Components
4 Realizing Expressions
5 Overall Realization
6 Conclusions
References
Reversible Circuit Optimization
Optimizing the Reversible Circuits Using Complementary Control Line Transformation
1 Introduction
2 Background
2.1 Reversible Logic Circuits
2.2 Quantum Cost of a Reversible Logic Circuit
3 Proposed Optimization Approach
3.1 Motivation
3.2 Basic Idea
3.3 The Gate Transformation Algorithm
3.4 Rule Based Optimization on Transformed Gate Netlist
3.5 Greedy Optimization
4 Simulation Results
5 Conclusion
References
An ESOP Based Cube Decomposition Technique for Reversible Circuits
1 Introduction
2 Background
2.1 Reversible Circuits
2.2 Exclusive-OR Sum-Of-Products (ESOP)
3 Related Work
4 Proposed Cube Decomposition Technique
4.1 General Idea
4.2 Generation of Primary and Secondary Gates
4.3 Algorithm for Cube Decomposition
5 Simulation Results and Comparisons
6 Conclusion
References
Controlled and Uncontrolled SWAP Gates in Reversible Logic Synthesis
1 Introduction
2 Realization of Negative-Controlled Fredkin Gate
3 SF Based Synthesis Approach
4 Comparison of NCT and SF Based Synthesis Approaches
5 Conclusion
References
Testing and Fault Tolerance
A Method to Reduce Resources for Quantum Error Correction
1 Introduction
2 Resource Requirement for 5-Qubit QECC
3 5-Qubit Quantum Error Detection Circuit
4 Savings in Resources by Our Proposed Method
5 Resource Savings Analysis
6 Conclusion
References
Test Pattern Generation Effort Evaluation of Reversible Circuits
1 Introduction
1.1 Reversible Circuits and Gates
1.2 Reversible Circuit Fault Models
1.3 Existing ATPG Solutions for Reversible Circuits
2 Proposed Work
2.1 Naive Test Pattern Generation
2.2 Exact (Minimal) Test Pattern Generation
2.3 Test Generation for Several Fault Models Using SAT Solver
3 Experimental Evaluation
4 Conclusion
References
Automatic Test Pattern Generation for Multiple Missing Gate Faults in Reversible Circuits
1 Introduction
2 Background
2.1 Reversible Circuits
2.2 Test of Reversible Circuits
3 ATPG for MMGF Detection
3.1 Test Generation for SMGFs
3.2 Dependency Analysis
3.3 MMGF Test Generation
3.4 Minimal Test Set Determination
4 Experimental Results
References
Quantum Circuits
Exact Global Reordering for Nearest Neighbor Quantum Circuits Using A*
1 Introduction
2 Nearest Neighbor Compliant Quantum Circuits
3 Global Reordering for Nearest Neighbor Quantum Circuits
4 Global Reordering Using A*
4.1 A* Algorithm
4.2 Straightforward Strategy
4.3 Elaborated Strategy
4.4 Discussion
5 Experimental Evaluation
6 Conclusions
References
Improved Decomposition of Multiple-Control Ternary Toffoli Gates Using Muthukrishnan-Stroud Quantum Gates
1 Introduction
2 Background
2.1 Ternary Reversible Gates
2.2 Ternary Elementary Gates
2.3 Existing Works in Ternary Reversible Logic Synthesis
3 Proposed Decomposition Approach Using M-S Gates
3.1 3-Input Ternary Toffoli Gate
3.2 Ternary Multiple-Control Toffoli (TMCT) Gate
4 Template Optimization and Results
5 Conclusion
References
Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions
1 Introduction
2 Quantum Multiple-Valued Decision Diagrams
3 Constructing QMDDs for Boolean Functionality
3.1 General Idea and Methodology
3.2 Generating the BDD of the Characteristic Function
3.3 Transforming the BDD into a QMDD
4 Constructing QMDDs for Quantum Functionality
5 Feasibility Study
6 Conclusions
References
Improving Synthesis of Reversible Circuits: Exploiting Redundancies in Paths and Nodes of QMDDs
1 Introduction
2 Background
2.1 Reversible Functions
2.2 Quantum Multiple-Valued Decision Diagrams (QMDDs)
2.3 Reversible Circuits
3 QMDD-Based Synthesis
4 Improving QMDD-Based Synthesis
5 Discussion
6 Experimental Results
7 Conclusion
References
Design of Efficient Quantum Circuits Using Nearest Neighbor Constraint in 2D Architecture
1 Introduction
2 Proposed Method
2.1 The Proposed Algorithm
2.2 Illustrative Example
3 Experimental Results
4 Conclusion
References
Erratum to: Designing Parity Preserving Reversible Circuits
Erratum to: Chapter "Designing Parity Preserving Reversible Circuits" in: I. Phillips and H. Rahaman (Eds.), Reversible Computation, LNCS 10301, DOI: 10.1007/978-3-319-59936-6_6
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