VLSI-SoC: At the Crossroads of Emerging Trends

Name: VLSI-SoC: At the Crossroads of Emerging Trends | 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised Selected Papers
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21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised Selected Papers

Alex Orailoglu H. Fatih Ugurdag Luís Miguel Silveira Martin Margala Ricardo Reis(Herausgeber*in)

Springer (Verlag)

Erschienen am 25. September 2015

XIV, 267 Seiten

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978-3-319-23799-2 (ISBN)

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Inhalt

Intro
Preface
Organization
Contents
Debugging Methods Through Identification of Appropriate Functions for Internal Gates
1 Introduction
2 Related Work: Finding a Configuration of LUTs Using Boolean SAT Solvers
3 Our Proposed Method to Correct Gate-Level Circuits
3.1 Overall Flow
3.2 Adding Variables to LUT Inputs
3.3 Using MUXs to Examine Multiple Additional Variables
3.4 Filtering Out Variables Based on Necessary Condition
4 Experimental Results
4.1 Experimental Setup
4.2 Simultaneous Examination on Multiple Variables Using Multiplexers
4.3 Candidate Variable Filtering Using the Necessary Condition
4.4 Applying Both Multiple Variable Examination and Candidate Filtering
4.5 Debugging Bugs in RTL Designs
5 Discussions for Extensions
6 Conclusions and Future Work
References
Gate Sizing Under Uncertainty
1 Introduction
2 Motivation
3 Related Work
4 Cell Library Energy and Delay
5 Technical Approach
5.1 Gate Sizing
5.2 Maximizing Yield
6 Experimental Results
6.1 Gate Sizing Under Switching Activity and IVC Uncertainty
6.2 Yield Optimization
7 Conclusion
References
New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure
1 Introduction
2 Preliminaries
2.1 AES
2.2 Differential Properties of AES
2.3 DFT Structure
3 Motivation and Challenges
3.1 State-of-the-Art Scan Attack
3.2 Limitations of the Existing Scan Attacks
3.3 Overcoming the Limitations of Existing Scan Attacks
4 Test-Mode-Only Attack on AES
4.1 Determining the Mapping Between Scan Cells and AES Input Words
4.2 Determining the Mapping Between Scan Cells and AES Input Bytes
4.3 Determining the Order of Bytes in a Word
4.4 Determining the Order of Bits in a Byte
4.5 Determining the AES Key
4.6 Attack Complexity Analysis
5 Existing Countermeasures
5.1 Insertion of Inverters in the Scan Path
5.2 Masking
5.3 Noise Injection in the Scan Output
5.4 On-chip Comparison of Responses
6 Proposed Countermeasure
7 Conclusion and Ongoing Work
References
Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Based on Accurate Cost Models
Abstract
1 Introduction
2 Hierarchical Architecture
3 Partitioning Impact Analysis
4 Power Model of Address Decoder
4.1 Basic Circuits of Address Decoder
4.2 Switching Activity
4.3 Energy Cost Related to Interconnects
4.4 Verification of Address Decoder Estimation Model
5 Power Model of the Memory Matrix
5.1 Four Circuit Templates
5.2 Verification of Memory Matrix Model
6 Optimization Results
7 Conclusion
References
Low-Power Low-Voltage Delta Sigma Modulator Using Switched-Capacitor Passive Filters
Abstract
1 Introduction
2 Passive Modulator Design Using CIFB Topology
2.1 System-Level Considerations
2.2 Low-Voltage Compatibility
2.3 Performance Limiting Factors
3 4-th Order Active-Passive Modulator
3.1 Architectural Design
3.2 Circuit-Level Design
4 Simulation Results
5 Comparison of the Power Efficiency
6 Summary
References
Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems
1 Introduction
2 Related Work
3 Problem Formulation
4 Noise Model
4.1 Noise Analysis for One Decision Variable
4.2 Extension to Multiple Stages
4.3 Extension to Multiple Inputs with Intermediate Quantization
5 Power Model
5.1 Datapath Power Analysis
5.2 Overhead Analysis
6 Results
6.1 FFT Optimization Results
6.2 IDCT Optimization Results
7 Summary and Conclusions
References
A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized
1 Introduction
1.1 Related Work
1.2 Summary of Contributions
1.3 Chapter Organization
2 Algorithm Details
2.1 Interest Point Detection
2.2 SKB Descriptor Calculation
2.3 Descriptor Matching
2.4 Descriptor Performance
3 Hardware Architecture
3.1 Image Pyramid and Line Buffer
3.2 SKB Core
3.3 Descriptor Matching
4 Results
4.1 ASIC Implementation of the Core
4.2 FPGA Implementation of the System
5 Conclusions
References
An FPGA-Based Real-Time System for 3D Stereo Matching, Combining Absolute Differences and Census with Aggregation and Belief Propagation
1 Introduction
2 Relevant Research
3 The Algorithm
4 Dimensioning of the FPGA Architecture
5 Design and Implementation
6 Performance Evaluation and Resource Utilization
7 Conclusions and Future Work
References
Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods
1 Introduction
2 The Set Covering Problem
2.1 Overview
2.2 Some Definitions
3 Minimization of Test Frequencies to Detect All the Faults of an Analog Circuit
3.1 Mathematical Formulation of the Problem as an SCP-C1P
3.2 Graph Formulation of the Problem
4 Approaches for Solving the Minimization Problem of Frequency Intervals
4.1 LP Approach
4.2 Interval Graph Approach
4.3 Numerical Example
4.4 Case of Multiple Detection Regions
5 Minimization of the Number of Test Measures Necessary for Detecting All the Faults of an Analog Circuit
6 Case-Study
7 Numerical Experiments
8 Conclusion
References
Partition-Based Faults Diagnosis of a VLIW Processor
Abstract
1 Introduction
2 VLIW Architecture Summary
3 Basics on Diagnosis
4 Diagnostic Test Program Generation
4.1 Classification
4.2 Brother Fragment Generation
5 Experimental Results
6 Equivalence Classes Analysis
6.1 VLIW Equivalence Classes Analysis
6.2 Maximization of the Diagnosability of the VLIW Partitions
6.3 Improved VLIW Partitioning
7 Conclusions and Future Work
References
Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware
Abstract
1 Introduction
2 Typical Look-up-Table Based Solution
3 Proposed Compression Scheme of the CLUTR Algorithm
4 Real-Time Decompression Hardware of CLUTR
5 Limitations of the CLUTR
6 The Compression Scheme of the E-CLUTR Algorithm
7 Real-Time Decompression Hardware of E-CLUTR
8 Implementation Results
9 Conclusion
References
A Flexible ASIC for Time-Domain Decision-Directed Channel Estimation in MIMO-OFDM Systems
1 Introduction
2 System Model
3 The TA-SAGE Algorithm
4 Algorithm Evaluation
5 TA-SAGE VLSI Architecture
5.1 Processing Schedule
5.2 Processing Units
5.3 Memory Architecture
6 Implementation Results
6.1 Full Feedback Architecture
6.2 Flexible Feedback Architecture
7 Conclusion
References
Author Index

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