A SystemC Based System On Chip Modelling and Design Methodology.- Using Transactional Level Models in a SoC Design Flow.- Refining a High Level SystemC Model.- An ASM Based SystemC Simulation Semantics.- SystemC as a Complete Design and Validation Environment.- System Level Performance Estimation of Multi-Processing, Multi-Threading SoC Architectures for Networking Applications.- SVE: A methodology for the Design of Protocol Dominated Digital Systems.- Object Oriented Hardware Design and Synthesis Based on SystemC 2.0.- Embedded Software Generation from SystemC for Platform Based Design.- SystemC-AMS: Rationales, State of the Art, and Examples.- Modeling and Refinement of Mixed-Signal Systems with SystemC.
