VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things

Name: VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things | 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers
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25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers

Michail Maniatakos Ibrahim (Abe) M. Elfadel Matteo Sonza Reorda H. Fatih Ugurdag José Monteiro Ricardo Reis(Herausgeber*in)

Springer (Verlag)

Erschienen am 16. Mai 2019

XIV, 257 Seiten

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978-3-030-15663-3 (ISBN)

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Inhalt

Intro
Preface
Organization
Contents
Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI
Abstract
1 Introduction
2 Background
3 Proposed Approach
3.1 Body-Bias Control to PMOS Transistors in VDDH Domain
3.2 SOTB Device
4 Results from Simulation
4.1 Simulation Setup
4.2 Voltage Limit for VDDL
4.3 Delay
4.4 Static Current
4.5 Active Energy
4.6 Influence by Process Variation
5 Results from Chip Measurements
5.1 Test Chip Design and Measurement Environment
5.2 Measured VDDLLIMIT
5.3 Measured Static Current and Power Dissipation
6 Conclusions and Future Work
Acknowledgment
References
Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs
Abstract
1 Introduction
2 Background
2.1 FinFET Characteristics
2.2 Static Random Access Memories
2.3 FinFET SRAM
2.4 Fault Models Associated to Resistive Defects
3 Simulation Setup
3.1 Modeled Defects
3.2 Evaluation of Defect Size on Fault Behavior
4 Results
4.1 Resistive-Open Defects
4.2 Resistive-Bridge Defects
4.3 Analysis Considering Different Operating Temperatures
4.4 Analysis Considering Different Nodes
5 Final Remarks
References
Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques
1 Introduction
2 Background and Motivation
2.1 STT-RAM
2.2 Coefficients of Write Variation and Lifetime
2.3 Motivation
3 Related Works
4 Proposed Wear Leveling Techniques
4.1 Fellow Sets with Static Reserve Part (FSSRP)
4.2 Fellow Sets with Dynamic Reserve Part (FSDRP)
5 Experimental Setup
6 Results and Analysis
6.1 Inter-set Write Variation
6.2 Reduction in Intra-set Write Variation
6.3 Lifetime Improvement
6.4 Invalidation/flushes
6.5 Energy Overhead
6.6 Performance
6.7 Storage Overhead
6.8 Parameter Comparison Analysis
7 Conclusion
References
A Wearable Neuro-Degenerative Diseases Classification System Using Human Gait Dynamics
Abstract
1 Introduction
1.1 Parkinson's Disease
1.2 Huntington's Disease
1.3 Amyotrophic Lateral Sclerosis (ALS)
1.4 The Fall Risk
1.5 Goal of This Work
2 Previous Work
3 Proposed Wearable NDD Detection System
4 NDD Classification Algorithm
5 Results and Discussion
6 Conclusion
Acknowledgement
References
Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applications
Abstract
1 Introduction
2 Related Work
3 Overview of Self-timed POR Circuit
3.1 Problem Statement
3.2 Self-timed POR Circuit
4 Components of Self-timed POR Circuit
4.1 Delayed VDD Generation
4.2 PCTRL Generation
4.3 NCTRL Generation
4.4 POR and the Feedback Circuit
5 SPICE Verification for Self-timed POR Circuit
6 Latch Based Self-feedback POR Circuit
7 Test Chip and Silicon Test Results
8 Conclusion
References
Pulsed Decimal Encoding for IoT Single-Channel Dynamic Signaling
1 Introduction
2 Review of PIC
3 Pulsed Decimal Communication
3.1 First Step: L1 Segmentation
3.2 Second Step: Encoding
3.3 Third Step: L2 Segmentation
3.4 Serialization
3.5 De-serialization, Decoding and Combination
3.6 PDC Example
4 PDC Protocol Analysis and Optimization
4.1 Preliminary Equations
4.2 General Case
4.3 Optimum Sub-Segment Size
4.4 Data Rate
4.5 Tolerance with Respect to Clock Variations
4.6 Automatic Protocol Configuration
4.7 Power Management
4.8 Reliability
5 Experimental Results
6 Conclusions
References
Electromigration Analysis of VLSI Circuits Using the Finite Element Method
1 Introduction
2 The Need for EM Analysis
3 Finite Element Method for EM Analysis
3.1 General Approach for EM Analysis
3.2 Benefits of FEM
3.3 Application in Physical Design
4 Problem Formulation: Limitations of FEM
4.1 Model Size Restriction
4.2 Atomic Scale Restriction
5 Our Approach: Pattern Verification
5.1 Basic Principle
5.2 Pattern Choice
5.3 From Pattern Verification to Full Chip Verification
6 Pattern Generation
6.1 Number of Needed Patterns
6.2 Generation of Sample Patterns
6.3 Restriction to Relevant Patterns
7 Verification
7.1 Example Simulations for Patterns and Their Combination
7.2 Full-Chip Analysis
7.3 Reduction in Simulation Time
8 Summary
References
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling
1 Introduction
1.1 Context
1.2 Motivation
1.3 Contribution
2 Related Works
2.1 Razor-Based Overhead Reduction
2.2 Existing Voltage Over-Scaling Approaches
3 Early Bird Sampling
4 Implementation Details
4.1 Tunable Delay Line (TDL)
4.2 Error Detection and Correction
4.3 Design Flow
5 Data-Driven Voltage Over-Scaling with EBS
5.1 DD-VOS Policies
6 Experimental Framework
6.1 Benchmarks and Testbenches
6.2 Quality Metrics
7 Results
7.1 Area Overhead
7.2 DD-VOS Improvement with EBS
7.3 EBS Characterization Under Different DD-VOS Implementations
8 Conclusions
References
Integrating Simulink, OpenVX, and ROS for Model-Based Design of Embedded Vision Applications
1 Introduction
2 Background and Related Work
3 The Model-Based Design Approach
3.1 OpenVX Toolbox for Simulink
3.2 Mapping Table Between OpenVX Primitives and Simulink Blocks
3.3 ROS Integration
4 Experimental Results
4.1 Image Stabilization
4.2 ORB Descriptor
5 Conclusion
References
Modeling and Evaluation of Application-Aware Dynamic Thermal Control in HPC Nodes
1 Introduction
2 Related Work
3 Workload and Thermal Modelling of HPC
3.1 Thermal Model
3.2 Power Model
3.3 Workload Model
3.4 Workload Distribution
4 HPC Optimal Thermal Control
4.1 Task Criticality Generator
4.2 The First Step Problem - FSP
4.3 The i-th Step Problem - ISP
5 Experimental Results
5.1 Emulation Framework
5.2 Evaluation of Prediction Horizons
5.3 Evaluation of the Task Criticality Generator
5.4 Performance Gain
6 Conclusion
References
Pushing the Limits Further: Sub-Atomic AES
1 Introduction
2 Background
2.1 The Advanced Encryption Standard
3 Basic Principles of the Architecture
3.1 Design Rationale
3.2 Area-Runtime Tradeoff
3.3 Serial MixColumns
3.4 SubBytes Implementation
4 Our Architecture
4.1 Architecture Overview
4.2 Individual Modules
5 Encryption vs. Decryption
6 Operation and Timing
7 An Even Smaller Variant
7.1 The Serial S-Box Architecture
7.2 Runtime Impact
8 Results
9 Conclusions
References
VLSI-SoC: An Enduring Tradition
Abstract
1 The Beginning
2 Years 90's
3 Years 2000's
4 Years 2010's
5 Conclusions
References
Author Index

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