This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
MIPS instruction set architecture (ISA) for application and for system programming
cache coherent memory system
store buffers in front of the data caches
interrupts and exceptions
memory management units (MMUs)
pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
I/O-interrupt controller and a disk
Reihe
Sprache
Verlagsort
Verlagsgruppe
Springer International Publishing
Illustrationen
1 s/w Abbildung
XV, 628 p. 1 illus.
Dateigröße
ISBN-13
978-3-030-43243-0 (9783030432430)
DOI
10.1007/978-3-030-43243-0
Schweitzer Klassifikation
Introductory material.- on hierarchical hardware design.- hardware library.- basic processor design.- pipelining.- cache memory systems.- interrupt mechanism.- self modification, instruction buffer and nondeterministic ISA.- memory management units.- store buffers.- multi-core processors.- advanced programmable interrupt controllers (APICs).- adding a disk.- I/O apic.
