Hardware Resources of AVR Microcontrollers

As noticed in the preface, the AVR microcontroller family is based on a new RISC architecture. In order to optimize code size, performance, and power consumption, the AVR architecture has incorporated a large fast-access register file and fast single-cycle instructions. The fast-access RISC register file consists of 32 general-purpose working resisters. Traditional accumulator-based architectures require large amounts of program code for data transfers between the accumulator and memory. With these 32 working registers—each of which acts as an accumulator—in AVR microcontrollers, these data transfers are eliminated.

The AVR microcontroller prefetches an instruction during the previous instruction execution and then executes in a single cycle. In other CISC- and RISC-like architectures, the external oscillator clock is divided down (by as much as 12 times) to the traditional internal execution cycle. The AVR microcontrollers execute an instruction in a single clock cycle and are the first true RISC machines in the 8-bit market.

The AVR architecture supports a complete spectrum of price performance, from simple small-pin-count controllers such as the AT90S1200 on the low end, to high-range devices with large on-chip memories such as the AT90S8515

The Harvard-style architecture directly addresses up to 8 Mbytes of program memory and 8 Mbytes of data memory. The register file is dual mapped and can be addressed as part of the on-chip SRAM memory to enable fast context switching.

2.1 Architectural Overview

Two different CPU models are used in the AVR microcontroller family. Atmel’s part numbering system gives the required information about the CPU model used in the each microcontroller device (see the Appendix for reference).

Figures 2-1 and 2-2 show block diagrams of the AT90S1200 (low end) and the AT90S8515 (high end) microcontrollers

Figure 2-1 Block diagram of AT90S1200 microcontroller.

Figure 2-2 Block diagram of AT90S8515 microcontroller.

Comparing Figures 2-1 and 2-2, we can find many common factors and some differences.

In all members of the AVR microcontroller family, the fast-access register file concept contains 32 8-bit general-purpose working registers with a single-clock-cycle access time. This means that during one single clock cycle, one

ALU (arithmetic logic unit) operation is executed. Two operands are fetched from the register file, the operation is executed, and the result is stored back in the register file—all in one clock cycle of 50 ns minimum.

In CPU model 1, six of the 32 registers can be used as three 16-bit indirect address register pointers for SRAM addressing, enabling efficient address calculations. In CPU model 0, only two registers build a 16-bit register. One of the three address pointers is also used as the address pointer for the constant table lookup function. These added function registers are the 16-bit X-register, Y-register, and Z-register.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost SRAM addresses, allowing them to be accessed as though they were ordinary memory locations.

With the relative jump and call instructions, the whole 4K address space is directly accessed. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the stack pointer (SP) in the reset routine (before subroutines or interrupts are executed). The 16-bit SP is read/write accessible in the I/O space.

The 256-byte data SRAM can be easily accessed through the four different addressing modes supported in the AVR architecture.

The I/O memory space contains 64 addresses for CPU peripheral functions such as control registers, timer/counters, A/D converters, and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.

The organization of program and data memory for an AT90S8515 microcontroller is shown in Figure 2-3 as a memory map. The program memory is executed with single-level pipelining. While one instruction is being executed, the next instruction is prefetched from the program memory. This concept enables instructions to be executed in every clock cycle. Figure 2-4 shows the timing conditions for this single-level pipelining.

Figure 2-3 Memory maps for program and data memory for AT90S8515.

Figure 2-4 Parallel instruction fetch and execution.

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register (SREG). All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt address vector, the higher the priority.

2.2 The Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all 32 general-purpose working registers. As Figure 2-5 shows, ALU operations between registers in the register file are executed within a single clock cycle.

Figure 2-5 Single-cycle ALU operation.

The ALU operations are divided into three main categories—arithmetic, logic, and bit functions. Some microcontrollers in the AVR microcontroller family will feature a hardware multiplier in the arithmetic part of the ALU.

2.3 Program and Data Memories

The AVR microcontroller uses a Harvard architecture concept, with separate memories and buses for program and data.

2.3.1 Downloadable Flash Program Memory

The program memory is in-system downloadable flash memory. The flash memory space of all microcontrollers of the AVR family is explained in detail in the hardware chapter. The different access methods to the program memory are explained in Chapter 3, which describes the handling of the hardware resources.

2.3.2 SRAM Data Memory

The data address space is organized in a maximum of four groups. The lower 96 bytes are reserved for register file and I/O registers in all devices of the AVR microcontroller family.

Microcontrollers with SRAM between internal and external SRAM will be distinguished. Figure 2-6 explains the organization of SRAM in an AT90S8515, for example. The parts of SRAM not available in all devices of the AVR microcontroller family are grayed. Microcontrollers have internal SRAM and can have external SRAM for enhancement. Between these both types must distinguished.

Figure 2-6 SRAM organization.

An access to the external SRAM occurs with the same instructions as for internal data SRAM access. When the internal data SRAM is accessed, the read and write strobe pins (/RD and /WR) are inactive during the whole access cycle. The external data SRAM physical address locations corresponding to the internal data SRAM addresses cannot be reached by the CPU. External SRAM operation is enabled by setting the SRE bit in the MCUCR register.

The PortA and PortC pins have alternative functions related to the optional external data SRAM. PortA can be configured to be the multiplexed low-order address/data bus during accesses to the external data memory, and PortC can be configured to be the high-order address byte.

Figure 2-7 shows read and write access to external SRAM without wait states.

Figure 2-7 External data SRAM memory cycle without wait state.

2.3.3 General-Purpose Register File

Figure 2-8 shows the structure of the general-purpose registers file in the CPU.

Figure 2-8 General-purpose register file.

All register operations have direct and single-cycle access to all registers. The only exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load immediate constant data. These instructions apply only to the registers R16..R31.

As shown in Figure 2-8, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user SRAM area. Although they are not physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X,Y, and Z registers can be set to index any register in the file for CPU...