Reconfigurable Computing: Architectures, Tools and Applications

Name: Reconfigurable Computing: Architectures, Tools and Applications | 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011, Proceedings
Brand: Springer
Price: 53.49 EUR
Availability: OnlineOnly

7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011, Proceedings

Andreas Koch Ram Krishnamurthy John McAllister Roger Woods Tarek El-Ghazawi(Herausgeber*in)

Springer (Verlag)

Erschienen am 15. März 2011

XIV, 398 Seiten

E-Book

PDF mit Wasserzeichen-DRM

Systemvoraussetzungen

978-3-642-19475-7 (ISBN)

53,49 €inkl. 7% MwSt.

Systemvoraussetzungen

für PDF mit Wasserzeichen-DRM

E-Book Einzellizenz

Als Download verfügbar

Beschreibung

Weitere Details

Weitere Ausgaben

Inhalt

Title Page
Preface
Organization
Table of Contents
Plenary Talks
Reconfigurable Computing for High Performance Networking Applications
Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform
Reconfigurable Accelerators I
A Reconfigurable Audio Beamforming Multi-Core Processor
Introduction
Background and Related Work
The Beamforming Architecture
The Reconfigurable Beamforming Microarchitecture
Hardware Prototype
Conclusions
References
A Regular Expression Matching Circuit Based on a Decomposed Automaton
Introduction
Regular Expression Matching for Network Applications
Related Work
Features of the Proposed Method
Regular Expression Matching Circuit Based on Automaton
Regular Expression Matching Circuit Based on Deterministic Finite Automaton
Regular Expression Matching Circuit Based on Non-deterministic Finite Automaton
Regular Expression Matching Circuit Based on NFA with String Transition
MNFAU
Realization of MNFAU
Complexity of Regular Expression Matching Circuit on Parallel Hardware Model
Theoretical Analysis
Analysis Using SNORT
FPGA Implementation
Conclusion
References
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios
Introduction
Previous Works
Multi-Core Crypto-Processor Architecture
Proposed Approach
General Architecture
Cryptographic Core Architecture
MCCP Operation
Packet Processing
Available Modes of Operation
Implementation of Cryptographic Algorithms
Task Allocation on MCCP
Channel Modelling
Hypothesis and Constraints
Task Allocation Algorithm
Performance Estimation of the Task Allocation Algorithm
Results
Implementation Results
Cryptographic Core Performances
MCCP Performances
Conclusion and Future Works
References
Design Tools
Application Specific Memory Access, Reuse and Reordering for SDRAM
Introduction
Background
SDRAM Memory
Previous Work
Example
Problem Description
Polytope Model
Memory Buffering and Reordering
Parametric Integer Linear Programming Formulation
Constraints
Output
Hardware Implementation
Results and Discussion
Conclusions and Future Work
References
Automatic Generation of FPGA-Specific Pipelined Accelerators
Introduction
Related Work
FloPoCo - A Tool for Generating Computational Kernels
Efficient Hardware Generation
Background
Motivating Examples
Step 1: Scheduling the Kernel
Step 2: Generating the Control FSM
Reality Check
Conclusion and Future Work
References
HLS Tools for FPGA: Faster Development with Better Performance
Introduction
HLS Tool, Algorithm and Parallelization
ImpulseC
Algorithm
Parallelization
Design Methodology and Architecture Description
Systolic Array Design
Design Optimizations
Clustering PEs
Performances
Platform Description
Design Variations Comparison
Comparison with Hand-Written HDL Code
State of the Art
Discussion
Fast and Reliable Design Process
Reusable and Portable Design
Obtaining Real Performance
Toward User Assisted Source to Source Transformation Tools
References
Posters 1
A (Fault-Tolerant)$^2$ Scheduler for Real-Time HW Tasks
Introduction: The R3TOS Approach
ATB: Area Time Response Balancing Scheduling Algorithm
Real-Time Hardware Task Model
Scheduling Real-Time Hardware Tasks with ATB
The Fault-Tolerant Architecture of the ATB Scheduler
Reliability and Performance Results
Conclusions
References
A Compact Gaussian Random Number Generator for Small Word Lengths
Introduction
Current Algorithms
Algorithm
Architecture
Statistical Tests
FPGA Implementation
Conclusion
References
Accurate Floating Point Arithmetic through Hardware Error-Free Transformations
Introduction
Atomic Operations
Accurate Addition/Subtraction
Accurate Multiplication
Accurate Vector Sums and Dot Products
Results
Conclusion
References
Active Storage Networks for Accelerating K-Means Data Clustering
Introduction
K-Means Data Clustering Algorithm
FPGA-Based K-Means Implementation
User Data Processing Stage
K-Means Implementation
Optimization
Parallelization Techniques
Results and Discussion
Conclusions
References
An FPGA Implementation for Texture Analysis Considering the Real-Time Requirements of Vision-Based Systems
Introduction
Overview of Texture Analysis
Hardware Implementation
Results
Conclusions and Future Works
References
CReAMS: An Embedded Multiprocessor Platform
Introduction
CReAMS Architecture
CReAMS Evaluation
Conclusions
References
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture
Introduction
REDEFINE
Partitioning the HyperOp
Edge betweenness Centrality
Experiments and Observations
Results
Conclusion
References
Reconfigurable Processors
A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection
Introduction
Related Work and Motivation
SIMD Array Architecture for FSD
FPGA-Based SIMD Processor Element Architecture
SIMD-Based FSD
Interleaved SIMD-Based FSD
Results and Discussion
Conclusion
References
Design, Implementation, and Verification of an Adaptable Processor in Lava HDL
Motivation and Previous Work
Lava: A Functional HDL
A Brief History
Lava Environment and Design Flow
Lava by Example
Making Lava Behave: Recipe
Designing a RISC Architecture
Basic Structure
PExpr Language
Verification
Synthesis and Test-Runs
Designing a CPU Extension
Conclusions
References
Towards an Adaptable Multiple-ISA Reconfigurable Processor
Introduction
Related Work
System Overview
Architecture Operation
First-Level Binary Translator
Second-Level System
Results
Simulation Environment
Binary Translation Data
Performance Evaluation
Area Overhead
Conclusions
References
Applications
FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments
Introduction
Previous Work
Algorithm Description
RICH and MDC Detectors in HADES
MDC Track Reconstruction
Cherenkov Ring Recognition
Implementation
Ring Recognition Unit Design
System Integration
Experimental Results
Implementation Results
Performance Measurements
Conclusion and Future Work
References
FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design
Introduction
Smith-Waterman Algorithm
Performance Analysis
Systolic Array Design
The Overview of an SWPE
Affine Gap Cost Function (a = ß = 0)
Experimental Results
Background for the Performance Assessment
Performance Comparison with Other FPGA Designs
Performance Evaluation of FPGA
CPU and GPUs
Conclusion
References
Index to Constant Weight Codeword Converter
Introduction
The Combinatorial Number System
Introduction
Circuit Implementation
Results
Complexity of Implementation
Trellis Generator
Introduction
Circuit Implementation
Results
Complexity of Implementation
Concluding Remarks
References
On-Chip Ego-Motion Estimation Based on Optical Flow
Introduction
Related Work
Mathematical Model of the Ego-Motion Algorithm
Phase-Based Algorithm
Ego-Motion Problem Statement
System Architecture
System Validation
Conclusions
Future Work
References
Device Architecture
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA
Introduction
Reference FPGA Architectures
Mesh-Based FPGA Architecture
Tree-Based FPGA Architecture
Software Flow
ASIF Generation
Efficient Logic Resource Sharing
Efficient Routing Resource Sharing
Experimental Results and Analysis
Effect of LUT and Arity Size on Tree-Based ASIF
Mesh and Tree ASIF Comparison
Conclusion
References
Dynamic V$_DD$ Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction
Introduction
Related Work
Structure of Our DRP
Array Structure
Context Control
Design and Implemention of Dynamic VDD Switching Technique on DRP
Supply-Line Selector for Dynamic V$_DD$ Switching
Level Shifter
Design Flow
Prototype Chip of Dynamic VDD Switching
Mapping Policy
Optimization Algorithm "PFCM"
Voltage Assignment
Evaluation
Energy Dissipation of PE
Evaluation of Energy Dissipation for 4×4 PE Array
Conclusion
References
MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays
Introduction
MEMS Interleaving ORGA and Its Method
MEMS Device
Interleaving Method
Experimental System
Experimental System
Experimental Results
Discussion
Conclusion
References
Posters 2
FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA
Introduction
Related Works
Our Approach
FaRM Architecture
Compression Technique
Operating Modes
Benchmarks
Bitstream Compression
Reconfiguration Overhead Estimation
Application
Future Works
Conclusion
References
Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications
Introduction
Related Work
Reconfigurable WSN Computing
Automatic Mapping of High-Level Descriptions to RTL
HaLoMote Architecture and Prototype Implementation
High-Level Synthesis Tool Flows
Word-Length Optimization
Hardware Synthesis
Experimental Evaluation
High-Level Synthesis: Latency vs. RCU Area Trade-Off
Latency and Area vs. RCU Power Draw Trade-Off
RCU Performance Evaluation
Conclusion
References
Hierarchical Optical Flow Estimation Architecture Using Color Cues
Introduction
Lucas and Kanade Optical Flow Estimation
Benchmarking
Hardware Implementation
Lucas and Kanade Optical Flow Core
Multiscale Architecture and System Performances
Conclusions
References
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power
Introduction
Architecture of Magnetic Look-Up Table (MLUT)
Simulated Performances
Radiation Hardness
Conclusion
References
Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers
Introduction
Sparse Row Addition - Merge Algorithm
Streaming Merge Core and Proposed Architecture
Merge Hardware Design
Streaming Platform
Results
Conclusion
References
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA
Introduction
Background
Interval Arithmetic
Ensuring Correct Rounding
The Solution of a System of Linear Equations
Parameterisable Interval Arithmetic Units
Enabling Correct Rounding
Parameterizable Interval Unit Implementation
Krawczyk Algorithm Implementation
Results
Comparison against an MPFR C Simulator
Conclusions
References
A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology
Introduction
eCPLD Architecture
ePLD - Dynamic Programmable AND-OR Structure
eConnect - Dynamic Programmable Interconnect Matrix
Implementation
Results
Conclusions
References
Reconfigurable Accelerators II
FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations
Introduction
Preliminary Algorithms and Related Work
Compressed Column Storage (CCS) Format [23]
Algorithms of Direct LU Factorization
Related Work
Algorithm Complexity
Complexity of Left-Looking Algorithm
Complexity of Right-Looking Algorithm
Proposed Architecture
Architecture for the Modified G/P Algorithm
Parallelized Architecture
Scalability
Experimental Result
Resource Consumption
Performance
Conclusions and Future Work
References
FPGA Optimizations for a Pipelined Floating-Point Exponential Unit
Introduction
Related Work
The EAU Architecture
Application-Specific Optimization
Evaluation and Performance
Hardware Verification
Application-Level Error Analysis
EAU Architecture Evaluation
Optimization Techniques Evaluation
Comparison with Other Implementations
Conclusion and Future Work
References
NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security
Introduction
Architecture
Handler Interface
Packet Forwarding
Handler Reconfiguration
Self-adaptation Strategy
Rule Representation
Fast Hierarchical Rule Matching
Packet Counter
Reconfiguration Candidate Selection
Implementation Details
Packet Forwarder and Adaptation Engine
Experimental Evaluation
Synthesis Results
Dynamic Partial Reconfiguration Results
Conclusion and Future Work
References
Methodology and Simulation
A Correlation Power Analysis Attack against Tate Pairing on FPGA
Introduction
Tate Pairing Algorithm
Tate Pairing Over $GF(2^m)$
Design of Tate Pairing Components Over $GF(2^m)$
Tate Pairing Architecture Over $GF(2^m)$
Tate Pairing in Identity Based Encryption
CPA Model and Attack
Hamming Distance Model
Correlation Power Analysis
CPA against Tate Pairing and Result Analysis
CPA against Single Multiplier Design
CPA against Maximum Area Design of Tate Pairing
Conclusion
References
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype
Introduction
The BeeFarm System
The Honeycomb Core: Extending Plasma
The BeeFarm Architecture
FPGA Resource Utilization
The BeeFarm Software
Comparison with SW Simulators
BeeFarm Multicore Performance of STM Benchmarks
The Experience and Trade-Offs in Hardware Emulation
Related Work
Conclusions and FutureWork
References
System Architecture
Architectural Support for Multithreading on Reconfigurable Hardware
Introduction
Related Work
Architectural and Microarchitectural Extensions
Software Support
Experimental Setup and Results
Conclusions and Future Work
References
High Performance Programmable FPGA Overlay for Digital Signal Processing
Introduction
Related Work
Programmable Overlay
Communication with Memory
The Array
Mapping
Results
Conclusions
References
Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture
Introduction
Related Work
Soft-Core Virtualization by a Dedicated Middleware
Structure of the Virtualization Middleware
Virtualization Procedure Using the Middleware
Benefits of the Virtualization Process
Application Example and Discussion
Conclusion and Further Work
References
Author Index

Systemvoraussetzungen

Als PDF speichern Als Link merken