VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability

Name: VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability | 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers
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24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers

Thomas Hollstein Jaan Raik Sergei Kostin Anton Tsertov Ian O'Connor Ricardo Reis(Herausgeber*in)

Springer (Verlag)

Erschienen am 31. August 2017

XIV, 233 Seiten

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978-3-319-67104-8 (ISBN)

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Inhalt

Intro
Preface
Organization
Contents
Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures
Abstract
1 Introduction
2 IoT Systems and Efficiency Bottlenecks
2.1 A General IoT System
2.2 Bottlenecks and Existing Efforts
3 Emerging Beyond-CMOS Devices
3.1 TFET
3.2 NCFET
4 New Opportunities Enabled by Emerging Devices, Circuits, and Architectures
4.1 Energy Harvesters and Sensors with Higher Efficiency
4.2 Analog Processing and Communication
4.3 Energy-Efficient Volatile Digital Logic
4.4 Energy-Efficient Nonvolatile Logic and Memory Circuits
4.5 Nonvolatile Computing Architectures
5 Future Work for IoT Using Emerging Devices
6 Conclusion
Acknowledgements
References
Logic with Unipolar Memristors - Circuits and Design Methodology
Abstract
1 Introduction
2 Unipolar Memristors
3 A Unipolar Memristive Logic Gate Example
3.1 Operation Principle
3.2 OR Gate
3.3 NOT Gate
3.4 Timing Considerations
3.5 Evaluation and Comparison
4 Methodology for Stateful Memristive Logic Design
5 Design Procedure for a Novel Unipolar Memristor Based Logic Gate
6 Conclusions
References
Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors
Abstract
1 Introduction
2 TFET Device and Its Characteristics
2.1 TFET Device Model
2.2 Comparison of TFET and MOSFET Operation
3 Hybrid TFET-MOSFET Circuits
3.1 Why Hybridization?
3.2 Proposed Heuristic Hybridization Algorithm
4 Results and Discussion
4.1 Simulation Framework
4.2 Comparison of Different Implementation Efficiencies
5 Conclusion
References
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits
1 Introduction
1.1 CMOS at the End of the Line
1.2 Candidates to Replace the CMOS Technology
1.3 Lack of Logic Synthesis Tools for PTL
1.4 Contribution of This Work
2 Multi-Gate Pass Logic
2.1 Pass-Gate Devices
2.2 Delay and Power Modeling of MGPL Circuits
3 Building MFPDS
3.1 Multi-function Decomposition
3.2 Multi-Function Pass Diagrams (MFPDs)
4 Algorithms
4.1 Building MFPD
4.2 Optimization
5 Simulation Results
5.1 Efficiency of Reduction Rules During MFPD Optimization
5.2 Compactness of the MFPD Model and Execution Time
5.3 Many Technologies, One Synthesis Methodology
5.4 Power and Performance Efficiency of MGPL Circuits
6 Conclusions
References
Digital Hardware Design Based on Metamodels and Model Transformations
1 Introduction
2 Model-Driven Architecture
2.1 The OMG Model-Driven Architecture Vision
2.2 Model-Driven Architecture for Hardware Development
3 Framework
3.1 The Overall Framework
3.2 Auxiliary Metamodels
4 The Model-of-Things Layer
5 The Model-of-Design Layer
5.1 The MetaRTL Metamodel
5.2 Templates-of-Design
5.3 Model-of-Things Instances for Template-of-Design Construction
5.4 Connectivity Resolution
6 The Model-of-View Layer
6.1 Automated View Generation from Model-of-View Instances
6.2 View Language Descriptions
7 Application and Results
7.1 Model-of-Things of the CPU Core Defined by the MetaRISC Metamodel
7.2 Assembly of a Template-of-Design for Micro-Architecture Generation
7.3 Results and Discussion
8 Related Approaches
9 Summary and Outlook
References
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings
1 Introduction
2 Clock-Domain Crossing Issues
2.1 Metastability and Multi-flops
2.2 Coherency with Gray-Encoding or Enable Control
2.3 Data Loss and Handshake
2.4 Performance with FIFO
3 Current Verification Approach
3.1 Structural Checks
3.2 Functional Checks
3.3 Limitation
3.4 Root Causes of Inconclusive Results
4 User-Aided Abstraction Refinement
4.1 Localization Abstractions
4.2 The Core Algorithm
4.3 Analysis of Abstract Counterexamples
4.4 Soundness, Completeness, Validity
5 Case Study
5.1 Asynchronous FIFO
5.2 CPU Subsystem
6 Related Work
7 Conclusion and Outlook
References
Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs
Abstract
1 Introduction
2 Background
3 Proposed Approach
3.1 Analysis Flow for Understanding SoC Behaviour
3.2 Processor Level Analysis and Classification of Functional States
3.3 Proposed Methodology for Generating Stress Programs
4 Experimental Results
4.1 Execution of Functional Programs
4.2 Automatic Generation of Functional Stress Programs
5 Conclusions
References
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping
1 Introduction
2 Previous Works
2.1 Approaching Ideal-DVFS
2.2 Within the Core Power Management
3 Implementing FINE-VH
3.1 Design and Optimization
3.2 Simulation and Emulation
4 Simulation Results
4.1 The RI5CY Benchmark
4.2 Experimental Set-Up
4.3 Results
5 Conclusions and Final Remarks
References
Earth Mover's Distance as a Comparison Metric for Analog Behavior
1 Introduction
2 Related Work
3 Earth Mover's Distance
3.1 Ground Distance
3.2 Algorithmic Concept
4 Assessment
4.1 Deviations
4.2 Comparable Algorithms
4.3 Results
5 Case Study
5.1 Application
5.2 Results
6 Conclusion and Outlook
References
Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO
1 Introduction
2 System Model
2.1 Linear Pre-coding at the Transmitter
3 Approximate Matrix Inversion
4 Proposed Method
5 Performance Analysis
6 Proposed Architecture
6.1 Seed Inversion Unit (X-1)
6.2 Seed Multiplication Unit (X-1Z)
6.3 Generic Multiplication Unit (IK-X-1Z)n
7 Timing Analysis
8 Implementation Results
9 Conclusion
References
A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA
1 Introduction
2 Background and Related Work
2.1 Stereo Matching Background
2.2 Related Work
3 Stereo Matching Algorithm
3.1 Algorithm Overview
3.2 Hardware-Oriented Optimization
4 Hardware Implementation
4.1 Architecture Overview
4.2 Pre-processing Stage
4.3 Stereo-Matching Stage
4.4 Post-precessing Stage
5 Experimental Results
5.1 Resource Utilization
5.2 Processing Speed
5.3 Quality Evaluation
6 Conclusion
References
Author Index

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