Architecture of Computing Systems - ARCS 2012

Name: Architecture of Computing Systems - ARCS 2012 | 25th International Conference, Munich, Germany, February 28 - March 2, 2012. Proceedings
Brand: Springer
Price: 53.49 EUR
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25th International Conference, Munich, Germany, February 28 - March 2, 2012. Proceedings

Andreas Herkersdorf Kay Römer Uwe Brinkschulte(Herausgeber*in)

Springer (Verlag)

Erschienen am 11. Februar 2012

XIII, 252 Seiten

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978-3-642-28293-5 (ISBN)

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Inhalt

Title
Preface
Organization
Table of Contents
Robustness and Fault Tolerance
Classification-Based Improvement of Application Robustness and Quality of Service in Probabilistic Computer Systems
Introduction
PCMOS
Component Models and Probabilistic Error Model
Implementation in MPARM
Annotations and Static Analysis
Evaluation
Experimental Environment
Qualitative Analysis: Applicability of Probabilistic Arithmetics
Quantitative Evaluation: Signal-to-Noise Ratio Using UVOS
Quantitative Evaluation: Signal-to-Noise Ratio Using BIVOS
Quantitative Evaluations: Summary
Related Work
Conclusions and Future Work
References
A Case Study on Error Resilient Architectures for Wireless Communication
Introduction
State of the Art
Error Resilience Exploration of an LTE Turbo Code Decoder
Multi-standard Channel Decoding ASIP
Exploration Framework
Timing Error Analysis on System Level
Soft-Error Analysis on System Level
Dynamic Error Mitigation
Conclusion
References
Using Dynamic Task Level Redundancy for OpenMP Fault Tolerance
Introduction
Related Work
Transient Faults
Transient Faults Categories
Software Based Transient Faults Detection and Recovery
OpenMP Fault Tolerance Using Tasks Redundancy
The OpenMP Tasking Model
A Flexible and Dynamic Redundancy Approach
Reliable Task
Inputs Replication
The Compare and Vote Runtime Function for Outputs Mismatch Detection and Recovery
Signals Handling for DUEs Detection and Recovery
Experimental Results
Fault Coverage Evaluation
Performance Evaluation
Comparison with the Static Redundant Threads Approach
Conclusion and Future Work
References
Power Aware Processing
A Very Fast and Quasi-accurate Power-State-Based System-Level Power Modeling Methodology
Introduction
Methodology Overview
Modeling
Architecture and Resource Modeling
Application Behavior Modeling
Power Behavior Modeling
Power and Performance Monitor
Experimental Results
Conclusions
References
Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands
Introduction
Task Mapping for Tiled CMPs
Problem Overview
Problem Definition
Task Mapping with Extremal Optimization
Fitness Functions
Experimental Results
Simulated Annealing and Extremal Optimization: Comparison
Power Optimization with EO
Conclusions
References
An Architecture for Power Management in Automotive Systems
Introduction
Related Work
Contribution
Vehicle Architecture
Functional Domains
Functional State Master
Power Domain
Power Distribution Master
Cybernetic Control System
Operating System Architecture
Transducing Model
Recursivity
Interaction and Implementation
Power Distribution
Functional State
Conclusion
References
Parallel Processing
Invasive MPI on Intel's Single-Chip Cloud Computer
Introduction
Related Work
RCCE
RCKMPI
The Invasive MPI Library
General Architecture
Invasive Process Manager
Invasive Extensions to MPI
Process Management Performance
Invasive Operations Performance
Invasive Numerical Integration
Conclusion
References
A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures
Introduction
Background
Proposal
Formal ILP Based Model
Heuristic Approach
Working Mode Ordering Metric
Experimental Results
Conclusions
References
Deterministic Execution Model on COTS Hardware
Introduction
Challenge for Embedding a Multicore COTS
Contribution
Related Work
Wcet of an Execution Slice
Reminder on Uniprocessor wcet Estimation
Application to a Sliced Architecture
Slicer
Wctt of a Communication Slice
Hardware Characteristics
Wctt Computation
Conclusion
References
Processor Cores
Design Principles for Synthesizable Processor Cores
Introduction
Related Work
The Architecture of Tinuso
Hardware Implementation
Forwarding
Memory Hierarchy
Results
Speed and Resources
Branch Performance Study
Conclusion
References
HPC Performance Domains on Multi-core Processors with Virtualization
Introduction
Related Work
Virtual Machines, HPC and Performance Domains on Multi-core Processors
Experimental Setup
Experimental Results
Conclusions
References
A Generic and Non-intrusive Profiling Methodology for SystemC Multi-core Platform Simulation Models
Introduction
Related Work
Trace Data Collection
Overview
Traceable Events
The NoCTrace Methodology
Automatic Design Analysis
Implementation
Architecture
SystemC Integration
Function Profile Generation
Application Example
Multi-core Platform Model
Parallel MJPEG Decoder
Results
Conclusion and Future Work
References
Optimization
Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging
Introduction
Scheduling Requirements
Motivating Example
Scheduling Requirements
Scheduling Framework
Scheduler Design
Dynamic Scheduling
Multi-GPU Support
Results
LDF Scheduling
Multi-GPU Support
Dynamic Scheduling
Conclusions
References
An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors
Introduction
Related Work
Model
Test Scenario
Sample Application
Implementations
Results
Ray Tracing Example
Projection
Discussion
Summary
References
Work Stealing Strategies for Parallel Stream Processing in Soft Real-Time Systems
Introduction
Related Work
Foundations
Work Stealing
Dataflow Process Networks
Work Stealing Strategies
Experimental Results
Summary and Conclusion
References
Design Space Exploration of Hybrid Ultra Low Power Branch Predictors
Introduction
Contributions
Overview
Motivating Example
Background
The Processor
The Simulator
Profiled BTFN and Hybrid Branch Prediction
Methodology
Workflow
The Bias Parameter
Evaluation
Related Work
Further Work
Conclusions
References
Communication and Memory
New Memory Organizations for 3D DRAM and PCMs
Introduction
Our Approach
Caches and Addressing
CMM
Victim CMM
Experimental Framework
Simulation Environment
Methodology
Results and Analysis
TLB Size
Page Size
Subpage Size
Pre-Fetch
Victim Size
Associativity
Related Work
Conclusion
References
Vertical Link On/Off Control Methods for Wireless 3-D NoCs
Introduction
Backgrounds
Cube-0: The First Trial of Wireless 3-D NoC
Related Works
On/Off Vertical Link Sleep Control
Sleep Control Method for URSL
Sleep Control method for BRHL
Sleep Control method for BRFL
Evaluations
Measurement on Vertical Links of Cube-0
Experiment Setup
Baseline Comparison Among URSL, BRFL and BRHL
Power Saving
Performance Overhead
Conclusions
References
SADmote: A Robust and Cost-Effective Device for Environmental Monitoring
Introduction
Motivation and Pilot Deployment
Related Work and Design Considerations
SADmote Hardware Design
SADmote Software Design
Evaluation
Energy Consumption
Radio Communication
The Initial Field Test of SADmote
SADmote Sensor Network Deployment
Conclusions and Future Work
References
Streamlined Network-on-Chip for Multicore Embedded Architectures
Introduction
Related Work
Prioritized Deflection Routing Algorithms
MULTIPATH Flit Priority
RADIAL Port Priority
Buffered Deflection Routing
CENTRAL Algorithm
RING Algorithm
Experimental Method and Results
Conclusions
References
Author Index

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