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This book constitutes the proceedings of the 27th International Symposium on VLSI Design and Test, VDAT 2023. The 32 regular papers and 16 short papers presented in this book are carefully reviewed and selected from 220 submissions. They are organized in topical sections as follows: Low-Power Integrated Circuits and Devices; FPGA-Based Design and Embedded Systems; Memory, Computing, and Processor Design; CAD for VLSI; Emerging Integrated Circuits and Systems; VLSI Testing and Security; and System-Level Design.
Prof. Anu Gupta received M.E and Ph.D. degrees from Birla Institute of Technology and Science (BITS) Pilani, in 1995 and 2003 respectively. In 1995, she joined BITS Pilani as an Assistant Lecturer. She was designated as Assistant Professor (in 2003), Associate Professor (in 2010), Professor (in 2016). She is an IEEE Senior member. Her research interests include low power, high performance analog/ digital/ mixed signal design for ASIC applications. Dr. Jai Gopal Pandey has been working as a Principal Scientist in Council of Scientific and Industrial Research - Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani, since 2005. He has received M.Tech. Degree in Electronics Design and Technology from U. P. Technical University, Lucknow, in 2003 and obtained Ph.D. in Electronics Engineering from Birla Institute of Technology and Science (BITS), Pilani, India in 2015. His research interests include high-performance architecture, SoCs, embedded systems, cryptography, and FPGA-based design. Dr. Pandey is an IETE Fellow, Senior Member of IEEE, and Life Member of the Semiconductor Society of India. Dr. Devesh Dwivedi is a distinguished professional, currently serving as the Director and India Site Leader at the Design Engineering Center of Excellence (CoE ) for GlobalFoundaries India. With a Ph.D. in Electronics Engineering from IIT BHU, Varanasi, Dr. Devesh has an impressive career spanning over 24 years in the industry. As a Senior IEEE Member, he has contributed significantly to the field with 70+ research publications, 15 US patents, and 2 trade secrets. He actively engages in various conferences, having chaired the IEEE CASS Bangalore Chapter. In the academic realm, Dr. Devesh is a respected visiting faculty member at IIT, NIT, and IIIT since 2012, holding the title of Distinguished Visiting Professor at IIT Roorkee. He has supervised 12 master's and 4 Ph.D. students and serves as a Board Member on the Industry-Academia Consulting Committee. Dr. Nitin Chaturvedi is Associate Professor in the Department of Electrical & Electronics Engineering, Birla Institute of Technology and Science, Pilani. He has more than 15 years of experience in academia and has contributed several publications in National and International Journals in the area of microelectronics and VLSI design. His interests include high performance cache architectures, CMOS VLSI design, asynchronous circuit design, non-volatile architectures for energy harvesting, in-memory computing, low-power neuromorphic circuit design and hardware security.
Analysis of SQNR Degradation in Noise-Shaped SAR Analog-to-Digital Converters at High Input Signal Amplitudes.- An improved clock booster circuit suitable for boost converters in energy harvesting environments.- A Current-Mode-Logic Based PFD-Charge Pump Circuit for Low Reference Spur PLLs.- An Energy Efficient Mixed Logic 2-to-4 Decoder for Embedded Memory Applications.- Analysis and Modeling of Self-Heating and Substrate Induced Transitions in 5 nm Stacked Nanosheet FET.- Chemisorption Analysis of NOx Sensor Using NF/Pr-AGNR: A DFT Investigation.- Design and Analysis of Differential Configuration based Active Inductor for 5G Sub-6GHz Applications.- A Dual-Mode High-Frequency Grounded Memristor Emulator Circuit.- Demonstration of Doped-HfO2 Ferroelectric based Double Layer Stacked NC FinFET.- High Precision Programmable Thermistor Linearization ASIC for Electro-Optical Payload Applications.- Design and Analysis of Low-Power Protection Circuits for LDO Regulators.- Preventing Costly Iterations by Delivering SoC Congestion Aware Standard Cell Lib using Pin Accessibility Checker.- High Throughput Multiple Device Diagnosis System for Hierarchical Test Designs.- Characterization of Multi-Vt Transistors for Analog IC Design in Sub-nanometer Technologies.- Design and Analysis of Modified Strong Arm Latch Comparator with Reduced Kickback Noise.- Construction of non-rectangular floor plans for properly triangulated planar graphs.
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