System Level Design from HW/SW to Memory for Embedded Systems

Name: System Level Design from HW/SW to Memory for Embedded Systems | 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3-6, 2015, Proceedings
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5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3-6, 2015, Proceedings

Marcelo Götz Gunar Schirner Marco Aurélio Wehrmeister Mohammad Abdullah Al Faruque Achim Rettberg(Herausgeber*in)

Springer (Verlag)

Erschienen am 16. April 2018

XII, 231 Seiten

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978-3-319-90023-0 (ISBN)

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Inhalt

Intro
Preface
IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS) November 3-6, 2015 Golden Tulip Conference Hotel, Foz do Iguacu, Brazil
Contents
Cyber-Physical Systems
Ontological User Modeling for Ambient Assisted Living Service Personalization
1 Introduction
2 Related Work
3 The AATUM Ontology
4 Use Case Study
5 Ontology Usage
5.1 Use Case 1
5.2 Use Case 2
6 Conclusion
References
Multi-Agent Based Implementation of an Embedded Image Processing System in FPGA for Precision Agriculture Using UAVs
1 Introduction
2 Reconfigurable Hardware Agent Framework
3 Case Study: UAV in Precision Agriculture
3.1 UAV and Multi-Agent Systems
3.2 Image Processing Algorithm
4 Results
5 Conclusion
References
Combining Service-Oriented Computing with Embedded Systems - A Robotics Case Study
1 Introduction
2 Case Study
Embedded System: Miniature Robot BeBot.
Application Scenario.
3 Service-Oriented Architecture
Overview.
Recipes.
Service Provider.
Services vs. Local Behaviours.
4 BeBot - Basic Node-Based Architecture
5 Integration: Service-Oriented Robotics
BeBot Wrapper: A Local Behaviour.
Overall System.
6 Conclusion
References
Integration of Robot Operating System and Ptolemy for Design of Real-Time Multi-robots Environments
1 Introduction
2 Related Works
3 Architecture
3.1 Robot Description
3.2 General Architecture
4 Methodology
4.1 Proof of Concept
4.2 Results
5 Conclusions and Future Works
References
System-Level Design
Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving
1 Introduction
2 Preliminaries
2.1 SystemC
2.2 UCLID
2.3 K-Inductive Invariant Verification
3 Related Work
4 Transformation from SystemC to UCLID
4.1 Assumptions
4.2 Representation of SystemC Designs in UCLID
4.3 Verification of SystemC Designs Using UCLID
5 Evaluation
6 Conclusion
References
Timed Path Conditions in MATLAB/Simulink
1 Introduction
2 Preliminaries
2.1 Path Conditions
2.2 MATLAB/Simulink
2.3 Information Flow Analysis
3 Related Work
4 Timed Path Conditions in MATLAB/Simulink
4.1 Running Example
4.2 Assumptions
4.3 Notations
4.4 Computation of Timed Path Conditions
5 Evaluation
6 Conclusion
References
Structural Contracts - Motivating Contracts to Ensure Extra-Functional Semantics
1 Introduction
2 Motivating Example
3 Related Work
4 Formal Basics
5 Structural Contracts
6 Proof of Concept
7 Conclusion
References
Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique
1 Introduction
2 Problem Domain
3 State-Based Timing Analysis
4 Impact Analysis Methodology
4.1 Concept
4.2 Combination with Abstractions
5 Evaluation
6 Conclusion and Outlook
References
Multi/Many-Core System Design
Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systems
1 Introduction
1.1 Hypervisor-Based Virtualization
1.2 Problem Statement
1.3 Contribution
2 Related Work
2.1 Multicore Scheduling
2.2 Hierarchical Scheduling
3 System Model
4 Hierarchical Scheduling with Precedence Constraints
4.1 Necessary Condition for Schedulability
4.2 Decomposition of Local Schedules
4.3 Multicore Scheduling of Time Partitions
5 Application Example
5.1 Decomposition of Local Schedules
5.2 Multicore Scheduling by Time Partitions
6 Conclusion
References
Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs
1 Introduction
2 Process Traces and Histories
2.1 Traces and Histories
2.2 Metrics
2.3 Trace Analysis
2.4 Results
3 Permutations of Mappings
3.1 Problem Formulation
3.2 Algorithmic Considerations
3.3 Experimental Results
4 Conclusion
References
Modeling and Analysis of SLDL-Captured NoC Abstractions
1 Introduction
2 Related Work
3 NoC Abstraction Models
4 Proposed NoC Models
4.1 Router Architecture
4.2 Packet Transmission
4.3 Arbitration Points
4.4 NoC Abstract Models: TLM and BFM
5 Experimental Results
5.1 BFM Validation
5.2 TLM Evaluation
6 Conclusion
References
Memory System Design
Taming the Memory Demand Complexity of Adaptive Vision Algorithms
1 Introduction
2 Related Work
3 Background
3.1 Data Separation
3.2 MoG Background Subtraction
4 Systematic Model Data Compression
4.1 System-Level Roadmap
4.2 Experimental Setup
4.3 Evaluation of Compression Schemes
4.4 Results Summary
5 Conclusions
References
HMC and DDR Performance Trade-offs
1 Introduction
2 Technological Constraints of Memory Designs
2.1 DRAM and DDR Architectures
2.2 HMC Architecture
3 Evaluation Methodology
3.1 Modeling DDR and HMC Simulation
3.2 Configuration Parameters and Workload
4 Experimental Results
4.1 SPEC-CPU2006 Results
4.2 SPEC-OMP2001 Results
4.3 Summary of Evaluations
5 Related Work
6 Conclusions and Future Work
References
Managing Cache Memory Resources in Adaptive Many-Core Systems
1 Introduction
2 Memory Clustering
3 Redistribution Policies and Mapping
4 Experimental Setup and Results
5 Related Work
6 Conclusion
References
Embedded HW/SW Design and Applications
A UML Profile to Couple the Production Code Generator TargetLink with UML Design Tools
1 Motivation
2 Related Work
3 TargetLink
3.1 TargetLink Data Dictionary Elements
3.2 Relationship Between TargetLink Elements
4 Prototype TargetLink Model in UML
4.1 Composite Structure Diagram
4.2 Prototype
5 Definition of the TargetLink UML Profile
5.1 Package Structure
5.2 Profile Structure
6 Information Exchange UML - TargetLink Data Dictionary
7 Conclusion and Future Work
References
Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables
1 Introduction
2 Related Work
3 Retargetable Profiling
4 Weight Calibration (WeiCal)
4.1 An Overview of the Framework
4.2 Linear Programming Formulation (LPF)
5 Implementation
6 Validation Through Synthetic Model
7 Experimental Results
8 Conclusion
References
Low Latency FPGA Implementation of Izhikevich-Neuron Model
1 Introduction
2 Izhikevich's Simple Model
2.1 Equations Model
2.2 Change of Variables
3 Neuron Implementation
3.1 One Neuron
3.2 Network for Tests and Metrics
4 Results
5 Conclusion
References
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
1 Introduction
2 Related Work
3 Accelerator Architecture
4 Reconfigurable Buffer Structures
5 Experimental Results
6 Conclusion
References
Author Index

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