Architecture of Computing Systems

Name: Architecture of Computing Systems | 37th International Conference, ARCS 2024, Potsdam, Germany, May 14-16, 2024, Proceedings
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37th International Conference, ARCS 2024, Potsdam, Germany, May 14-16, 2024, Proceedings

Dietmar Fey Benno Stabernack Stefan Lankes Mathias Pacher Thilo Pionteck(Herausgeber*in)

Springer (Verlag)

Erschienen am 1. August 2024

XIX, 360 Seiten

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978-3-031-66146-4 (ISBN)

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Beschreibung

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Inhalt

Intro
Preface
Organization
Keynote Talks
Strategies towards Green HPC - Environmental Analysis and Applied Ecodesign
Co-Designing Processor Arrays and their Compiler - "The Whole is Greater than the Sum of the Parts"
Contents
Progress in Neural Networks
nAIxt: A Light-Weight Processor Architecture for Efficient Computation of Neuron Models
1 Introduction
2 Processor
2.1 Initial Architecture
3 Toolchain
3.1 Assembler
3.2 Scheduler
3.3 Software Pipelining
4 Results and Discussion
4.1 Benchmarks
4.2 Design Space Exploration
4.3 Comparison
4.4 Analysis and Optimization
5 Conclusion
References
An Approach Towards Distributed DNN Training on FPGA Clusters
1 Introduction
2 Related Work
3 Background
4 Tool Flow
5 Evaluation
6 Conclusion
References
The Power of Training: How Different Neural Network Setups Influence the Energy Demand
1 Introduction
2 Related Works
2.1 Energy Tracking
2.2 Hyperparameter Selection
3 Methodology
3.1 Experiment Setup
3.2 Training Regime
3.3 Learning Paradigm
4 Training Regime Results
5 Pretraining Learning Paradigm Results
6 Multitask Learning Paradigm Results
7 Correlation with High-End Consumer Hardware
8 Conclusion
References
Organic Computing
An Efficient Multi Quantile Regression Network with Ad Hoc Prevention of Quantile Crossing
1 Introduction
2 Related Work
2.1 Quantile Regression Neural Network
2.2 Composite Quantile Regression Neural Network
2.3 Monotone Composite Quantile Regression Neural Network
2.4 Differentiable Sorting
3 Methodology
3.1 Sorted Composite Quantile Regression Neural Network
3.2 Theoretical Complexity Analysis
3.3 Datasets
3.4 Experiment 1
3.5 Experiment 2
4 Results and Discussion
4.1 Experiment 1
4.2 Experiment 2
5 Conclusion
References
Modifiable Artificial DNA - Change Your System's ADNA at Any Time
1 Introduction
2 Related Work
3 Artificial Hormone System and Artificial DNA
4 Modifications
4.1 Task Structure and Applicable Modifications
4.2 ADNA at Runtime
4.3 Communicating and Applying the Changes
5 Experimental Evaluation
5.1 Setup and Environment
5.2 Predictions
5.3 Hormone Cycle Length Dependency
5.4 Modifications on a Fixed ADNA
5.5 Expanding to Larger ADNAs
6 Future Work
6.1 Blank Tasks
6.2 Two Phase Modification
7 Conclusion
References
From Structured to Unstructured: A Comparative Analysis of Computer Vision and Graph Models in Solving Mesh-Based PDEs
1 Introduction
2 Related Work
3 Methodology and Data
3.1 Models
3.2 Datasets
3.3 Experimental Setup
4 Results and Discussion
5 Conclusion
References
Enhancing Maritime Behaviour Analysis Through Novel Feature Engineering and Digital Shadow Modelling: A Case Study in the Kiel Fjord
1 Introduction
2 Background
2.1 Maritime Navigation Behaviour Analysis
2.2 SV-NBA Framework for Spatio-Temporal Analysis in Maritime Applications
3 Approach
3.1 Spatio-Temporal Feature Extraction
3.2 Trajectory Mining
3.3 Behaviour Analysis and Visualisation
4 Experiments
4.1 Experimental Setup
4.2 Experimental Results
5 Analysis and Discussion
6 Conclusion
A Appendix
References
Synthesizing Training Data for Intelligent Weed Control Systems Using Generative AI
1 Introduction
2 Background
2.1 Image Augmentation
2.2 Segment Anything Model (SAM)
2.3 Diffusion Models (DMs)
3 Methodological Approach
3.1 Data Set
3.2 Data Transformation
3.3 Image Generation
4 Evaluation
5 Discussion
6 Conclusion and Outlook
References
Towards the Online Reconfiguration of a Dependable Distributed On-Board Computer
1 Introduction
1.1 ScOSA - The Scalable On-Board Computer Architecture for Space Avionics
1.2 Reconfiguration Services
2 Related Work
3 Design of the Online Algorithm
3.1 Scheduling
4 Evaluation
5 Results and Discussion
5.1 Timing Analysis
5.2 Network Analysis
5.3 Memory Analysis
6 Conclusions
References
An Organic Computing Approach for CARLA Simulator
1 Introduction
2 Related Work
3 ADNA-Based Organic Computing
3.1 Artificial Hormone System - AHS
3.2 Artificial DNA - ADNA
4 CARLA Automotive Simulator
5 pyDNAAHS: Organic Computing Interface for CARLA
6 Proof of Concept
7 Conclusion
References
Computer Architecture Co-Design
Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity
1 Introduction
2 System Model
3 Problem Statement
4 Proposed Solution
4.1 Reducing Energy for FPGA Configuration Phase
4.2 Minimize Number of Configurations by Idle-Waiting
4.3 Analytical Model
5 Experiments and Results
5.1 Experiments Setup
5.2 Experiment 1: Optimization on Energy for FPGA Configuration
5.3 Experiment 2: Idle-Waiting vs On-Off Strategies
5.4 Experiment 3: Optimization on the Idle-Waiting Strategy
6 Related Work
7 Conclusion and Future Work
References
On-the-Fly CT Image Pre-processing on MPSoC-FPGAs
1 Introduction
2 Background: CT Imaging
3 CT Pre-processing Phase: Proposed Optimizations
4 Realization
5 Discussion
6 Summary
References
AccProf: Increasing the Accuracy of Embedded Application Profiling Using FPGAs
1 Introduction
2 Related Work
3 AccProf - Design and Implementation
3.1 Instrumentation Engine Based on LLVM
3.2 FPGA Hardware - HLS Driven
3.3 The SeL4 Microkernel and Pass - HLS Communication
4 Evaluation
4.1 Testbed
4.2 The STREAM Benchmark
4.3 Embench Benchark Suite
4.4 Discussion
5 Conclusions
References
Accelerating WebAssembly Interpreters in Embedded Systems Through Hardware-Assisted Dispatching
1 Introduction
2 Related Work
3 WebAssembly
4 Computed GoTo
5 Accelerator Design
5.1 Hardware Design
5.2 Software Integration
6 Evaluation
6.1 Binary Size
6.2 Effect on Benchmark Runtime
6.3 Acceleration by WASM Opcode
7 Conclusion and Outlook
References
Exploring the ARM Coherent Mesh Network Topology
1 Introduction
2 Background: The ARM Coherent Mesh Network, CMN
3 Extracting the ARM CMN Topology
3.1 Mesh Size and Node Locations
3.2 CPU Core and Peripheral Locations
4 Measurements and Results
4.1 Synthetic Benchmarks
4.2 LULESH Benchmark
4.3 Discussion
5 Related Works
6 Conclusion
References
Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level
1 Introduction
2 BSD Introduction and FA Based Circuitry for the Adder
3 Implementation on Physical Layout Level
4 Evaluation
4.1 Timing
4.2 Area
4.3 Power
5 Summary and Future Work
References
Progress in HPC
Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC
1 Introduction
2 Background
3 NUMA Architecture: Modeling and Exploration
3.1 Modeling NUMA Topologies with Gem5
3.2 NUMA Modeling in VPSim
4 Evaluation
4.1 Performance for Different NoC Bandwidths
4.2 STREAM TRIAD on a 4-NUMA Node GPP
4.3 Application Performance Characterization Using VPSim
4.4 Memory Page Migration in NUMA Systems
5 Conclusion and Perspectives
References
A Hierarchical Modeling Approach for Assessing the Reliability and Performability of Burst Buffers
1 Introduction
2 Related Work and Background
2.1 Generalized Stochastic Petri Nets
2.2 Reliability Block Diagrams
3 Proposed Models
3.1 Reliability Model
3.2 Performability Model
3.3 Dynamic Mean Time to Failure Model
3.4 Overall Proposed Performability Method for BBs
4 Evaluation
4.1 Exploratory Analysis
4.2 Models Validation
4.3 Experimental Results
5 Conclusion
References
Generative-Based Algorithm for Data Clustering on Hybrid Classical-Quantum NISQ Architecture
1 Motivations and Objectives
2 Related Works
3 Our Approach and Implementation
3.1 From Neural Network to QCBM
3.2 Focus on Machine Learning Algorithm: QCBM & EM Clustering
3.3 Specificities of Task Distribution on a CPU-QPU Architecture
3.4 Implementation with Qiskit Framework
4 Experiments
4.1 Comparing Models
4.2 Impact of Quantum Noise
4.3 Test on Real Quantum Hardware
5 Conclusion and Perspective
References
Computer Architecture
Improving Memory Dependence Prediction with Static Analysis
1 Introduction
1.1 Memory Dependence Prediction in Out-of-Order Execution
1.2 ``Predict No Dependency'' Load Labels
1.3 Contributions
2 Finding PND Labels with LLVM
2.1 Analysis Algorithm
2.2 Analysis Limitations
2.3 Compiler to CPU Communication
3 Simulation and Workflow
3.1 Experimental Design
3.2 Simulating PND Labels in Gem5
3.3 Gem5 CPU Configuration and the Store Sets Predictor
3.4 Simulation Workflow
4 Evaluation
4.1 Coverage
4.2 CPI over CPU Sizes
4.3 Discussion
5 Threats to Validity
6 Related Work
7 Conclusions
8 Future Work
References
Atalanta: Open-Source RISC-V Microcontroller for Rust-Based Hard Real-Time Systems
1 Introduction
2 Background and Related Work
2.1 Real-Time Interrupt-Driven Concurrency Framework
2.2 Interrupt Architectures in RISC-V
2.3 Interrupt Latency
3 Architecture
3.1 RT-Ibex
3.2 Microcontroller
4 Evaluation
4.1 Implementation
4.2 Analysis
4.3 Comparison
4.4 Discussion
5 Conclusions
References
Dependability and Fault Tolerance
Software-Based Erasure-Tolerant Coding with Buffering and Compression
1 Introduction
1.1 Concept of Low-Rate Codes with Compression
1.2 Related Work
1.3 Structure and Aim of the Paper
2 Interaction of Buffering and Coding
2.1 Buffer Architecture
2.2 Selection of Buffered Input Data for Encoding
2.3 Code Properties and Insights from Implementation
3 Experimental Evaluation of Overhead
4 Reliability Study
5 Summary
References
Determination of Optimal H-Matrices for 2-Bit Error Correcting Codes
1 Introduction
2 A 2-Bit Error Detecting BCH-Code Cannot Be Extended
3 Extension of a 2-Bit Error Detecting BCH-Code with Included Parity
4 Optimal and Near Optimal H-Matrices Generated by a Computer Program
5 Concrete Computer Generated H-Matrices
5.1 Optimal H-Matrix with 4 Check Bits
5.2 Optimal H-Matrix with 5 Check Bits
5.3 Optimal H-Matrix with 6 Check Bits
5.4 Optimal H-Matrix with 7 Check Bits
6 Heuristic Search
7 Results
8 Summary
References
Author Index

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