Advanced Low-Power Digital Circuit Techniques
presents several novel high performance digital circuit designs that emphasize low-power and low-voltage operation. These circuits represent a wide range of circuits that are used in state-of-the-art VLSI systems and hence serve as good examples for low-power design. Each chapter contains a brief introduction that serves as a quick background and gives the motivation behind the design. Each chapter also ends with a summary that briefly explains the contributions contained therein. This makes the book very readable. The reader can skim through the chapters very quickly to get a feel for the design problems presented in the book and the solutions proposed by the authors. Examples of circuits used in systems where low-power is important from reliability and portability points of view (such as general-purpose and DSP processors) are presented in Chapters 2, 3 and 4. Chapters 5 and 7 give examples of circuits used in systems where reliability and more system integration are the main driving forces behind lowering the power consumption. Chapter 6 gives an example of a general purpose high-performance low-power circuit design.
Advanced Low-Power Digital Circuit Techniques
is a real designer's book. It investigates alternative circuit styles, as well as architectural alternatives, and gives quantitative results for comparison in realistic technologies. Several of the circuits presented have been fabricated so that simulations can be checked. The circuits covered are the most important building blocks for many designs, so the text will be of direct use to designers. MOS designs are covered, as well as BiCMOS, and there are several novel circuits.
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ISBN-13
978-1-4419-8546-0 (9781441985460)
DOI
10.1007/978-1-4419-8546-0
Schweitzer Klassifikation
1 Low-Power VLSI Design.- 1.1 Power Estimation and Evaluation for Digital VLSI Circuits.- 1.2 Low-Power Impact on Process and Technology.- 1.3 This Book.- References.- 2 Low-Power High-Performance Adders.- 2.1 Introduction.- 2.2 Architecture.- 2.3 Circuit Design and Implementation.- 2.4 Optimization Using Variable Block Size Combination.- 2.5 Simulation Strategy.- 2.6 Circuit performance.- 2.7 Layout Strategy.- 2.8 Experimental Results.- 2.9 Summary.- References.- Low-Power High-Performance Multipliers.- 3.1 Introduction.- 3.2 Review of Parallel Multipliers.- 3.3 Multiplier Architecture and Simulation Method.- 3.4 Multiplier Cell.- 3.5 Booth Encoder.- 3.6 Add Cell.- 3.7 CSA.- 3.8 6-Bit Multiplier.- 3.9 Summary.- References.- Low-Power Register File.- 4.1 Introduction.- 4.2 Architecture and Simulation Procedure.- 4.3 Memory Cell Circuit.- 4.4 Write Circuitry.- 4.5 Read Circuitry.- 4.6 Decoder Circuit.- 4.7 32x32-bit Register File.- 4.8 Summary.- References.- Low-Power Embedded Bicmos/ECL Srams.- 5.1 Introduction.- 5.2 16 Mb+ SRAMs Front-end Optimization.- 5.3 The Novel W-ORing and Level-Translation Circuits.- 5.4 The Novel Self-Resetting WL Decoder and Driver.- 5.5 The Novel Latched Sense-Amplifier.- 5.6 Chapter Summary.- References.- BICMOS On-Chip Drivers.- 6.1 Introduction.- 6.2 The Novel Full-Swing BiCMOS Circuit Technique.- Performance Comparisons.- 6.4 Design of the Feedback Circuitry.- 6.5 Chapter Summary.- References.- Inter-Chip Low-Voltage-Swing Transceivers.- 7.1 Introduction.- 7.2 Low-Power ECL/CML Dynamic Circuit Techniques.- 7.3 The Universal Transceiver (Receiver/Driver).- 7.4 Chapter Summary.- References.
