Reconfigurable Computing: Architectures, Tools and Applications

Name: Reconfigurable Computing: Architectures, Tools and Applications | 8th International Symposium, ARC 2012, Hongkong, China, March 19-23, 2012, Proceedings
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8th International Symposium, ARC 2012, Hongkong, China, March 19-23, 2012, Proceedings

Oliver Choy Ray Cheung Peter Athanas Kentaro Sano(Herausgeber*in)

Springer (Verlag)

1. Auflage

Erschienen am 22. März 2012

XIV, 386 Seiten

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Inhalt

Title Page
Preface
Organization
Table of Contents
Applied RC Design Methods and Tools
Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration
Introduction
RTR Background
TLUT Method
SRL Reconfiguration
Automatic Linking of SRLs into Reconfiguration Chains
Problem Definition
Previous Work on the Multiple Travelling Salesman Problem
Proposed Method for Solving the Constrained mTSP
Experimental Results
Results Using the VPR Tools
Results Using the Xilinx Tools
Conclusion
References
Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration
Introduction
Related Work
PR Floorplanning Considerations
Architecture Considerations
PR Operation
Required Reconfigurable Area
Actual Reconfigurable Area
Resource Wastage
Wirelength
Static Logic
Proposed Floorplanner
Columnar Kernel Tessellation
Case Study
Conclusion
References
Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array
Introduction
Related Work
Systolic Computational-Memory Architecture
Stencil Computation
Systolic Computational-Memory Architecture
Processing Elements
Execution Model of PE
Domain-Specific Language and Compiler
Domain-Specific Language for Stencil Computation
Overview of Compiler for DSLSC
Parallelism Analysis Stage
Graph-Folding Stage
Partitioning Stage
Scheduling Stage
Implementation and Results
Conclusions
References
Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture
Introduction
Related Work
SIMD Reconfigurable Architecture
Architecture
Compilation
Minimizing Bank Conflicts in SIMD Mapping
Microcore Mapping
Macrocore Mapping
Experiments
Effect of SIMD Mapping: Performance and Configuration Size
Macrocore Mapping Comparisons
Compilation Time
Conclusion
References
Table-Based Division by Small Integer Constants
Introduction
Euclidean Division of an Integer by a Small Constant
Notations
Algorithm
Memory Structures in Current FPGAs
Division of a Floating-Point Number by a Small Integer Constant
Normalization
Rounding
Results and Comparison
Integer Division
Floating-Point Division
Comparison with Previous Work
Conclusion
References
Heterogeneous Systems for Energy Efficient Scientific Computing
Introduction
Workload Allocation Formulation
Exploration Approach
System Metrics
Design Exploration Flow
Experiment Setup
Experimental Results
Conclusion
References
The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms
Introduction
Research Context
Q2 Profiling Framework
Quipu Modeling Approach
QUAD Dynamic Memory Profiling Toolset
Partitioning Methodology
Case Study
Experimental Results
Conclusions
References
Applied RC Architectures
PPMC: A Programmable Pattern Based Memory Controller
Introduction
Programmable Pattern Based Memory Controller (PPMC)
PPMC Architecture
Data Access Pattern
Vector Access Pattern (AoS or SoA)
Tiling Access
Evaluations of PPMC
The System Architecture
Test Applications
Results and Discussion
Related Work
Conclusion
References
A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor
Introduction
Related Work
The -VEX VLIW Processor
Task Migration Scheme
Interrupts System
Run-Time Task Migration for VLIW Multi-core Processor
Experimental Results
Conclusions
References
Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration
Introduction
Related Work
System Architecture
Microarchitecture
CPU
VIREMENT Reconfigurable Datapath
VIREMENT Control Unit
Structure of the Dynamic Compiler Engine (DCE)
Code Generation Process
Evaluation
Performance Evaluation
Area Evaluation
Conclusions
References
Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs
Introduction
Bit Parallel Multiplier
Digit Serial Multiplier
LUT Based Complexity Analysis for LSD Multiplier
Hardware Architecture
Multiplier Core (MC) Module
Main Reduction (MR) Module
Final Reduction (FR) Module
Complexity Summary and Evaluation
LUT Consumption Comparison
Critical Delay Comparison
Optimum Digit Size on FPGAs
Conclusion
References
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs
Introduction
Related Work
ScalableCore System
Overall Concept and Architecture
Architectures of ScalableCore Unit and Memory Unit
System Level Functions
System Behavior
Implementation of ScalableCore System with 100 FPGAs
Evaluation
Resource Usage
Simulation Speed
Case Study: Task Allocation on Tile Architecture
Conclusion
References
Scalable Memory Hierarchies for Embedded Manycore Systems
Introduction
Memory Hierarchies
Experiments and Results
Experimental Setup
Weak Scalability Analysis
Strong Scalability Analysis
Related Work
Conclusions
References
Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays
Introduction
Triple Module Redundancy (TMR) on Conventional ORGA Architectures
Robust Ability of Conventional ORGA Architectures
Triple Module Redundancy (TMR)
Unexpected Reconfiguration Procedure Detection and Recovery Methods
Three-ORGA Implementation Method (1)
Reconfiguration Area Limitation Method (2)
Robust TMR Laser Driver Circuit
Experiments
Prototype VLSI Chip
Hologram Calculation Method
Hologram Generation
Experimental System and Results
Conclusion
References
A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters
Introduction
Architecture
RBB Switch Box
RBB Logic Block
Routing Architecture
Dual-VT Pathfinder Algorithm
Further Leakage Power Mitigation Strategies
Slack Reclamation
Unused Resources
Experimental Methodology and Results
Conclusion
Future Work
References
Applied RC Applications
Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations
Introduction
Background
Multi-level Customisation Framework
Application Specialisation Flow
Result
Conclusion
References
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU
Introduction
Virus Scanning System
Related Works
Contributions of the Paper
A Virus Scanning Based on Two-Stage Matching
Definitions
ClamAV Virus Pattern
Virus Scanning Engine Using Two-Stage Matching
Subpattern Length m
Binary CAM Emulator Using Four Index Generation Units
Index Generation Function
Finite Input Memory Machine to Detect a Subpattern
Index Generation Unit for FIMM
Capability of the Index Generation Unit
Realization of the Index Generation Function Using Parallel Sieve Method Nakahara-DSD2009
Realization of the Index Generation Function Using Four IGUs sasao-iwls-2010
Discussion
Experimental Results
Minimum Subpattern Length m
Implementation Results
Conclusion and Comments
References
Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration
Introduction
Related Work
UPACS
MUSCL Algorithm
Partial Reconfiguration
Implementation
Evaluation
Resources Utilization
Power Consumption
Configuration Time
Performance
Conclusion
References
Parallel Tempering MCMC Acceleration Using Reconfigurable Hardware
Introduction
Related Work
Parallel Tempering
System Architecture
Description
Using Custom Arithmetic Precision
Bayesian Inference for Mixture Models
Description
Implementation of the Probability Evaluation Block
Results
Comparison to CPU and GPGPU Performance and Scalability
Performance Evaluation under Custom Precision
Conclusion
References
A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem
Introduction
Background
Symmetric Extremal Eigenvalue Problem
Sequential Runtime Analysis
Related Work
Parallelizing the Lanczos Method on FPGAs
Parallelism Potential
System Architecture
Solving Multiple Extremal Eigenvalue Problems
Methodology
Results
FPGA Performance Evaluation
Comparison with Multi-core and GPU
Future Work
Conclusion
References
Optimising Performance of Quadrature Methods with Reduced Precision
Introduction
Background
Optimisation Modeling
Accuracy Analysis
Performance Modeling
Optimisation Objective Equation
Optimisation Algorithm and Methodology
Case Studies
Discrete Moving Barrier Option Pricer
Multi-dimensional European Option pricer
Genz's ``Discontinuous'' Benchmark Integral
Result and Evaluation
Performance Comparison
Energy Comparison
Conclusion
References
Critical Issues in Applied RC
Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform
Introduction
Related Work
Course Organization
Learning Objectives
Lecture Content
Introduction
System Design
Target Architectures for Hardware/Software Systems
Models
Hardware/Software Interfaces
Hardware/Software Performance Estimation and Partitioning
Compilation, Code Generation and Synthesis
Reconfigurable Computing
Practical Exercises
Altium Designer and NanoBoard 3000
Lab Exercises
Group Projects
Conclusions
References
Securely Sealing Multi-FPGA Systems
Introduction
Security Objectives for Hardware Systems
State of the Art in FPGA Security
Security Features of Modern FPGAs
Prior Academic Work
Threat Model, Assumptions and Requirements
Configuration Integrity Checking
Integrity Check at System Startup
Periodic Integrity Check at Runtime
Electronic Sealing of Multi-chip Systems
Symmetric Authentication and Central Security Module
Pairwise Authentication
Authentication Based on a Ring Topology
Implementation Considerations
Conclusions
References
FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores
Introduction
Background
Floating Point Representation
The IEEE Standard
Hardware Test Suites
Existing FPGA IP-Cores
Test Framework
Adapting Paranoia to FPGA Core Generators
Paranoia on an FPGA
Basic Arithmetic
Exponentiation
Underflow and Overflow
Results
Basic Arithmetic
Exponentiation
Underflow and Overflow
Conclusion
References
High Performance Reconfigurable Architecture for Double Precision Floating Point Division
Introduction
Design Approach
Hardware Implementations of FPA Division
Results and Comparisons
Conclusions and Future Works
References
Posters
A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems
Introduction
Modular-Based Assembly
A Modular-Based Assembly Framework
The Library Builder
The Design Assembler
Implementation Details
Preliminary Results
Conclusion and Future Work
References
Constructing Cluster of Simple FPGA Boards for Cryptologic Computations
Introduction
Proposed Architecture for FPGA Cluster
Our Scheme and Its Operational Steps
Using FPGA Cluster for Acceleration of Cryptographic Computations and Cryptanalysis
Implementation and Experimental Results
Conclusion
References
Reconfigurable Multicore Architecture for Dynamic Processor Reallocation
Introduction
Proposed Architecture
DyaReMA
DyaReMA with Reduced Number of Meshes
Segmented DyaReMA
Experimental Results and Analysis
DyaReMA Simulation Results
Synthesis Models
Conclusion
References
Efficient Communication for FPGA Clusters
Introduction
Broadcast Design
Performance Model
Results
Conclusion
References
Performance Analysis of Reconfigurable Processors Using MVA Analysis
Introduction
Related Work
Proposed Models for Processing Elements
GPP Queuing Models
Proposed Models for Reconfigurable Processing Elements
Proposed Model for a Hybrid Processing Element
Performance Evaluation and Experimental Results
Result Discussion
Conclusion
References
PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs
Introduction
Related Work
Problem Formulation
Simulated Annealing Algorithm Framework
Cost Models
Optimization of PR Region
Experiments
Conclusions and Future Work
References
A Connection Router for the Dynamic Reconfiguration of FPGAs
Introduction
Background
Tunable Circuit
The tcon Routing Problem and TROUTE
Limitations of TROUTE
The Connection Router
Experiments and Results
Conclusion and Future Work
References
R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip
Introduction
R-NoC Architecture and Protocols
R-NoC Architecture Description
Structured Routing Path and Reconfiguration
R-NoC Protocols
R-NoC Routers and Network Topology
Router Design
R-NoC Topology Design and Routing
Software Simulation for R-NoC
Conclusions
References
Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms
Introduction
Brief Description of Keccak
Implementation
Datapath of Keccak
Novel Arithmetic Architecture for Keccak Compression Function
Implementation Results
Comparison with Previous Work
Conclusion
References
CRAIS: A Crossbar Based Adaptive Interconnection Scheme
Introduction
CRAIS Architecture
Hardware Interconnection and Communication Protocol
CRAIS Work Flow
State Transfer
FPGA Prototype and Preliminary Results
FPGA Prototype
Hardware Overheads
Conclusion and Future Work
References
Author Index

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