Application-Driven Architecture Synthesis
describes the state of the art of architectural synthesis for complex real-time processing.
In order to deal with the stringent timing requirements and the intricacies of complex real-time signal and data processing, target architecture styles and target application domains have been adopted to make the synthesis approach feasible. These approaches are also heavily application-driven, which is illustrated by many realistic demonstrations, used as examples in the book.
The focus is on domains where application-specific solutions are attractive, such as significant parts of audio, telecom, instrumentation, speech, robotics, medical and automotive processing, image and video processing, TV, multi-media, radar, sonar.
Application-Driven Architecture Synthesis
is of interest to both academics and senior design engineers and CAD managers in industry. It provides an excellent overview of what capabilities to expect from future practical design tools, and includes an extensive bibliography.
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ISBN-13
978-1-4615-3242-2 (9781461532422)
DOI
10.1007/978-1-4615-3242-2
Schweitzer Klassifikation
1 Application-driven synthesis methodologies for real-time processor architectures.- 1 Problem description.- 2 State-of-the-art and beyond.- 3 Contribution of this book.- 4 System specification model.- 5 Synthesis of array processors.- 6 Synthesis of multiplexed processors.- 7 Chapter overview.- 8 Conclusion.- References.- 2 Behavioral specification for synthesis.- 1 Introduction.- 2 The ASCIS data flow graph.- 3 Input specification languages.- 4 Conclusion.- References.- 3 Formal methods for solving the algebraic path problem.- 1 Introduction.- 2 The algebraic path problem.- 3 Pioneering systolic APP designs.- 4 Advanced systolic APP designs.- 5 Extending synthesis methods.- 6 Partitioning issues.- 7 Conclusion.- References.- 4 HiFi: from parallel algorithm to fixed-size VLSI processor array.- 1 Introduction.- 2 Design philosophy.- 3 Algorithmic specification.- 4 Architecture model.- 5 Design trajectory.- 6 Fixed-size architecture design.- 7 Conclusion.- References.- 5 On the design of two-level pipelined processor arrays.- 1 Introduction.- 2 Transformation of nested loops to UREs.- 3 Word-level array design.- 4 Bit-level array design.- 5 Conclusion.- References.- 6 Regular array synthesis for image and video applications.- 1 Introduction.- 2 A design script.- 3 A real-life video application.- 4 Deriving the initial description.- 5 Re-indexing transformations.- 6 Localizing transformations.- 7 Space-time mapping.- 8 Conclusion.- References.- 7 Memory and data-path mapping for image and video applications.- 1 Introduction.- 2 High-level memory management.- 3 High-level data-path mapping.- 4 Conclusion.- References.- 8 Automatic synthesis for mechatronic applications.- 1 Introduction.- 2 System overview.- 3 Application domain and target architecture.- 4 Behavioral synthesis transformations.- 5 Structural synthesis.- 6 Results.- 7 Conclusion.- References.- 9 Synthesis for control-flow-dominated machines.- 1 Introduction.- 2 Integration with existing design environments.- 3 An overview of AMICAL.- 4 Mixing manual and automatic design.- 5 A design example.- 6 Conclusion.- References.- 10 Controller synthesis and verification.- 1 Introduction.- 2 Architecture selection.- 3 Architecture implementation.- 4 Formal verification of finite state machines.- 5 Verification of implementation.- 6 Conclusion.- References.
