Advanced Nanoscale MOSFET Architectures

Name: Advanced Nanoscale MOSFET Architectures | Current Trends and Future Perspectives
Brand: Wiley-ISTE
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Current Trends and Future Perspectives

Kalyan Biswas Angsuman Sarkar(Herausgeber*in)

Wiley-ISTE (Verlag)

1. Auflage

Erschienen am 23. Mai 2024

336 Seiten

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978-1-394-18898-7 (ISBN)

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Inhalt

Cover
Title Page
Copyright
Contents
About the Editors
List of Contributors
Preface
Acknowledgments
Chapter 1 Emerging MOSFET Technologies
1.1 Introduction: Transistor Action
1.2 MOSFET Scaling
1.3 Challenges in Scaling the MOSFET
1.4 Emerging MOSFET Architectures
1.4.1 Tunnel FET
1.4.2 Nanowire FET
1.4.3 Nanosheet FET
1.4.4 Negative Capacitance FET
1.4.5 Graphene FET
1.4.6 III-V Material-based MOSFETS
1.4.7 HEMT
1.4.8 Strain Engineered MOSFETs
1.5 Organization of this Book
References
Chapter 2 MOSFET: Device Physics and Operation
2.1 Introduction to MOSFET
2.2 Advantages of MOSFET
2.3 Applications of MOSFETs
2.4 Types of MOSFETs
2.4.1 P-Channel and N-Channel MOSFET
2.4.2 MOSFET Working Operation
2.5 Band Diagram of MOSFET
2.5.1 Accumulation Layer
2.5.2 Depletion Layer
2.5.3 Inversion Layer
2.6 MOSFET Regions of Operation
2.6.1 N-Channel Depletion MOSFET
2.6.2 P-Channel depletion MOSFET
2.6.3 Operating Regions of P-Channel Depletion MOSFET
2.6.4 Enhancement MOSFET
2.6.5 N-Channel Enhancement MOSFET
2.6.6 P-Channel Enhancement MOSFET
2.7 Scaling of MOSFET
2.7.1 Types of Scaling
2.8 Short-channel Effects
2.8.1 Drain-induced Barrier Lowering
2.8.2 Gate-induced Drain Leakage
2.9 Body Bias Effect
2.9.1 Salient Feature of Body Bias
2.9.2 Significance of Body Bias
2.9.3 Body Bias Verification
2.10 Advancement of MOSFET Structures
References
Chapter 3 High-? Dielectrics in Next Generation VLSI/Mixed Signal Circuits
3.1 Introduction to Gate Dielectrics
3.2 High-? Dielectrics in Metal-Oxide-Semiconductor Capacitors
3.3 High-? Dielectrics in Metal Insulator Metal (MIM) Capacitors
3.3.1 High-? Dielectrics for Mixed Signal Circuits
3.3.2 High-? Dielectrics as Stacks for Resistive Random Access Memories
3.4 MOSFETs Scaling and the Need of High-?
3.5 High-? Dielectrics in Next Generation Transistors
3.5.1 Planar-Nano Scale Field Effect Transistor
3.5.2 Silicon on Insulator
3.5.3 FIN Field Effect Transistor
3.5.4 Tunnel Field Effect Transistor
3.5.5 Negative Capacitance Field Effect Transistor
References
Chapter 4 Consequential Effects of Trap Charges on Dielectric Defects for MU-G FET
4.1 Introduction
4.2 TID Effects Overview
4.3 Application Area of Device for TID Effect Analysis
4.4 Near the Earth: Trapped Radiation
4.5 Ionizing Radiation Effect in Silicon Dioxide (SiO2)
4.6 TID Effects in CMOS
4.7 TID Effects in Bipolar Devices
4.8 Understanding and Modeling a-SiO2 Physics
4.9 Hydrogen (H2) Reaction with Trapped Charges at Insulator
4.10 Pre-Existing Trap Density and their Respective Location
4.11 Use of High-K Dielectric in MU-G FET
4.12 Properties of Trap in the High-K with Interfacial Layer
4.13 Trap Extraction Techniques
4.13.1 Capacitance Inversion Technique (CIT)
4.13.2 Charge Pumping Technique (CPT)
4.14 Conclusion
References
Chapter 5 Strain Engineering for Highly Scaled MOSFETs
5.1 Introduction
5.2 Simulation Approach
5.2.1 Strain Mapping
5.2.2 Mechanical Strain Modeling
5.2.3 Piezoresistivity Effect
5.2.4 Strain Induced Carrier Mobility
5.3 Case Study
5.3.1 Stress/Strain Engineering in Bulk-Si FinFETs
5.3.1.1 Performance Analysis of Bulk-Si FinFET
5.3.1.2 Effects of Fin Geometry Variations
5.3.2 Nanosheet
5.3.2.1 Impact of Mechanical Stress
5.3.2.2 Strained Engineering with Embedded Source/Drain Stressor
5.3.3 Extremely Thin SOI MOSFETs
5.4 Conclusions
References
Chapter 6 TCAD Analysis of Linearity Performance on Modified Ferroelectric Layer in FET Device with Spacer
6.1 Introduction
6.2 Simulation and Structure of Device
6.3 Results and Analysis
6.4 Conclusion
Acknowledgment
References
Chapter 7 Electrically Doped Nano Devices: A First Principle Paradigm
7.1 Introduction
7.2 Electrical Doping
7.3 First Principle
7.3.1 DFT
7.3.2 NEGF
7.4 Molecular Simulation
7.5 Conclusion
References
Chapter 8 Tunnel FET: Principles and Operations
8.1 Introduction to Quantum Mechanics and Principles of Tunneling
8.2 Tunnel Field-Effect Transistor
8.3 Challenges of Tunnel Field-Effect Transistor
8.3.1 Low On-state Current
8.3.2 Drain-Induced Barrier Thinning Effect
8.3.3 Ambipolarity
8.3.4 Trap-Assisted Tunneling
8.4 Techniques for Improving Electrical Performance of Tunnel Field-Effect Transistor
8.4.1 Doping Engineering
8.4.2 Material Engineering
8.4.3 Geometry and Structure Engineering
8.5 Conclusion
References
Chapter 9 GaN Devices for Optoelectronics Applications
9.1 Introduction
9.2 Properties of GaN-Based Material
9.2.1 Bandgap of GaN
9.2.2 Critical Electric Field of GaN
9.2.3 ON-resistance of GaN
9.2.4 Two-dimensional Electron Gas Formation at AlGaN/GaN Interface
9.3 GaN LEDs
9.3.1 Different Colors LEDs
9.3.2 µ-LEDs
9.3.3 Micro-LEDs with GaN-based N-doped Quantum Barriers
9.3.4 Blue Light Emission in GaN-based LEDs
9.3.5 Characteristics
9.4 GaN Lasers
9.4.1 Blue Laser Diodes
9.5 GaN HEMTs for Optoelectronics
9.6 GaN Sensors
References
Chapter 10 First Principles Theoretical Design on Graphene-Based Field-Effect Transistors
10.1 Introduction
10.2 Graphene
10.2.1 Electronic Structure
10.2.2 Scanning Tunneling Microscopy
10.2.3 Electronic Transport
10.3 Graphene/h-BN Hybrid Structure
10.3.1 Atomic Structure
10.3.2 Structure and Energetics
10.3.3 Electronic Structure
10.3.4 Scanning Tunneling Microscopy
10.4 Conclusions
Acknowledgments
References
Chapter 11 Performance Analysis of Nanosheet Transistors for Analog ICs
11.1 Introduction
11.2 Evolution of Nanosheet Transistors
11.2.1 Short-Channel Effects and Their Mitigation
11.2.2 The FinFET Technology
11.2.3 Advent of Nanosheet Transistors
11.3 TCAD Modeling of Nanosheet Transistor
11.4 Transistor's Analog Performance Parameters
11.4.1 Transconductance
11.4.2 Output Conductance
11.4.3 Intrinsic Gain
11.4.4 Transconductance Efficiency
11.4.5 Discharge Time
11.4.6 Small Signal Capacitances and AC Model
11.4.7 Transit Frequency
11.5 Challenges and Perspectives of Modern Analog Design
References
Chapter 12 Low-Power Analog Amplifier Design using MOS Transistor in the Weak Inversion Mode
12.1 Introduction
12.2 Review of the Theory of Weak Inversion Mode Operation of MOS Transistor
12.2.1 Drain Current Model in the Weak Inversion Mode
12.2.2 Concept of Inversion Coefficient
12.2.3 Parameter Extraction
12.2.3.1 Technology Current Constant Io
12.2.3.2 Sub-threshold Swing Factor ?
12.2.4 Small Signal Parameters in Weak Inversion Region
12.3 Design Steps for Transistor Sizing Using the IC
12.4 Design Examples
12.4.1 Design of a Common Source Amplifier
12.4.2 Single-Ended Operational Transconductance Amplifier
12.4.2.1 Implementation and Simulation Result
12.5 Summary
References
Chapter 13 Ultra-conductive Junctionless Tunnel Field-effect Transistor-based Biosensor with Negative Capacitance
13.1 Introduction
13.2 Importance of SS and ION/IOFF in Biosensing
13.3 Importance of Dopingless Source and Drain in High Conductivity
13.4 Relation of Negative Capacitance with Non-hysteresis and Effect on Biosensing
13.5 Variation of Source Material on Biosensing
13.6 Importance of Dual Gate and Ferroelectricity on Biosensing
13.7 Effect of Dual Material Gate on Biosensing
References
Chapter 14 Conclusion and Future Perspectives
14.1 Applications
14.1.1 Opportunities in Big Data
14.1.2 Fight Against Environment Change
14.1.3 Creation of Graphene
14.1.4 Nano Systems
14.1.5 Nanosensors
14.2 Some Recent Developments
14.3 Future Perspectives
14.4 Conclusion
References
Index
EULA

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