Architecture of Computing Systems - ARCS 2011

Name: Architecture of Computing Systems - ARCS 2011 | 24th International Conference, Lake Como, Italy, February 24-25, 2011. Proceedings
Brand: Springer
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24th International Conference, Lake Como, Italy, February 24-25, 2011. Proceedings

Mladen Berekovic William Fornaciari Uwe Brinkschulte Cristina Silvano(Herausgeber*in)

Springer (Verlag)

Erschienen am 14. Februar 2011

XIII, 271 Seiten

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978-3-642-19137-4 (ISBN)

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Inhalt

Title
Preface
Organization
Table of Contents
Customization and Application Specific Accelerators
A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing Systems
Introduction
Related Work
Sample Application
Combined Analysis
General Concept
Implementation
General Result Interpretation
Combined Analysis of the Sample Application
Implementations
FPGA-Based Implementation
GPU-Based Implementation
Conclusions
References
Scalability Evaluation of a Polymorphic Register File: A CG Case Study
Introduction
Background and Related Work
Case Study Scenario
Simulation Results and Analysis
Conclusions
References
Experiences with String Matching on the Fermi Architecture
Introduction
Related Work
CUDA GPUs
Aho-Corasick
Algorithm Implementation
Experimental Evaluation
Conclusions
References
Multi/Many-Core Architectures
Using Amdahl's Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric Processors
Introduction
Related Works
Amdahl's Law and Functionally Asymmetric Many-Core Architecture
Extensible Processor and Functionally Asymmetric Many-Core Architecture
Combination of TLP and ILP
Functional Asymmetric Architecture to Improve the Occupation Rate
Constraints of the Theoretical Analysis
Summary and Conclusion
References
Application-Aware Power Saving for Online Transaction Processing Using Dynamic Voltage and Frequency Scaling in a Multicore Environment
Introduction
Power Saving in Online Transaction Processing
Online Transaction Processing
Application-Aware Power Saving
Application-Aware Dynamic Scaling for Online Transaction Processing
Dynamic Voltage and Frequency Scaling
Application-Aware Dynamic Frequency Scaling for Online Transaction Processing
Experimental Environment and Basic Measurements
Experimental Environment
Basic Measurements
Evaluation of Application-Aware Power Saving
Synthetic Workload
Real-World Workload
Related Work
Conclusion
References
Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration
Introduction and Related Work
2D/3D Image Registration
Application
Parallelization Strategies
Frameworks
Framework Evaluation
Usability Evaluation
Performance Evaluation
Overhead Estimation
Conclusions
References
Adaptive System Architectures
Emulating Transactional Memory on FPGA Multiprocessors
Introduction
Related Work
Software Interface
Architectures
Master/Slave Architecture
Distributed Architecture
Experimental Evaluation
Conclusion
References
Architecture of an Adaptive Test System Built on FPGAs
Introduction
Motivation
System Architecture
General Idea
The Layer Concept
Device Models
Automation
Main Hardware Components
Implementation
Test Scenario
Processor, Communication Interface, and DUT Interface
Automatic Generation Flow
Results
Conclusion and Future Work
References
An Extensible Framework for Context-Aware Smart Environments
Introduction
Related Work
Framework Design
Context Modelling
Pipe-and-Filter Architecture
Context Interpretation Rules
Architecture Deployment Language
Case Study - A Smart Classroom Scenario
Conclusions
References
Processor Architectures
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3
Introduction
UTLEON3 Processor Architecture
Analysis
Impact of the Pipelined Long-Latency Operations
Impact of the Non-pipelined Long-Latency Operations
Experimental Evaluation on the Microthreaded Processor
Conclusions
References
A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware
Introduction
Related Work
The Dynamic Instruction Scratchpad
D-ISP Architecture
D-ISP Implementation Details
Evaluation of Performance Impact
D-ISP Hardware Effort Estimation
Conclusions
References
Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy
Introduction
Related Work
Prefetching
Memory Controllers
Prefetch Scheduling Strategies
Opportunistic Prefetch Scheduling
Methodology
Results
Performance
Maximum Performance Regression
Accuracy and Coverage
Increasing DRAM Bandwidth
Discussion
Conclusion
References
Memory Architectures Optimisation
Compiler-Assisted Selection of a Software Transactional Memory System
Introduction
Related Work
Detection of Memory Access Patterns in Transactions
Data Aggregation
Analysis Phase
Decision
Evaluation
Experimental Setup
Test Cases
STAMP Benchmarks
Conclusion and Outlook
References
An Instruction to Accelerate Software Caches
Introduction
Multidimensional Software Cache
MDSC Accelerator
Experimental Methodology
Experimental Results
LookUp_SC
GLCM Results
MC Results
Conclusions
References
Memory-, Bandwidth-, and Power-Aware Multi-core for a Graph Database Workload
Introduction
Clustered Multicore Architecture
DEX Application
Experimental Setup
Experimental Results
Memory Access Time
Bandwidth
Power Consumption
Combined Analysis
Related Work
Conclusions
References
Organic and Autonomic Computing
A Light-Weight Approach for Online State Classification of Self-organizing Parallel Systems
Motivation
Related Work
Hierarchical, Distributed Monitoring-Infrastructure
Low-Level Monitoring
High-Level Monitoring
Rule-Based State Evaluation and Classification
Data Structures
Rule Layout
Online Learning Phase for Rule Creation
State Evaluation and Classification
Update of Rules at Runtime
Evaluation / Results
Initial Classification
Overhead Evaluation
Rule-Update at Runtime
Optimization Example
Conclusion and Outlook
References
Towards Organic Active Vision Systems for Visual Surveillance
Introduction
Related Work
Architecture
Networked System Architecture
Active Vision Node Architecture
The Multi-robot Routing Problem
A Self-organizing Approach to the Multi-robot Routing Problem: ALMA
Phase 1: Initial Assignment of Target Requests
Phase 2: Conflict Resolving
Experiments and Results
Conclusion
References
Emergent Behaviour in Collaborative Indoor Localisation: An Example of Self-organisation in Ubiquitous Sensing Systems
Introduction
Experimental Evaluation
Scenario Description
Used Sensor Systems and Processing
Experiment Results
Simulation
Scenario Description
The Model
Simulation Results
Conclusion
References
Network-on-Chip Architectures
An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation
Introduction
Conventional On-Chip Router Architecture and Motivation
Basic Design
Motivation
Proposed On-the-fly VC Allocation Architecture
On-the-fly VC Allocation
Operation of Packet Transfer
Evaluation
Implementation Results
Latency and Throughput
Conclusion
References
Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths
Introduction
The Proposed NoC
Resource Partitioning Mechanism
NoC Architecture
The Reconfiguration Procedure
Shortcut Reconfiguration Algorithm
Experimental Results
Synthetic Traffic Results
SPLASH-II Results
Conclusion
References
A Learning-Based Approach to the Automated Design of MPSoC Networks
Introduction
Goals and Contributions
Motivating Example
Overview
Experimental System Architecture
NoC Architecture
Methodology
Extracting Performance Data
Machine Learning Algorithm
Benchmarks
Results
Related Work
Conclusions and Future Work
References
Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa
Introduction
Related Work
Transformation Concept
Variant 0: Reference Design
Variant 1: Buffered Approach
Variant 2: Timed Approach
Variant 3: Urgency Approach
Test Setup
Experimental Results
End-to-End Latency
Ethernet/IP Bandwidth
Resource Utilization
Vehicle Network Configuration
Conclusion
References
Author Index

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