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Communication between engineers, their managers, suppliers and customers relies on the existence of a common understanding for the meaning of terms. While this is not normally a problem, it has proved to be a significant roadblock in the EDA industry where terms are created as required by any number of people, multiple terms are coined for the same thing, or even worse, the same term is used for many different things. This taxonomy identifies all of the significant terms used by an industry and provides a structural framework in which those terms can be defined and their relationship to other terms identified. The origins of this work go back to 1995 with a government-sponsored program called RASSP. At the termination of their work, VSIA picked up their work and developed it further. Three new taxonomies were introduced by VSIA for additional facets of the system design and development process. Since role of VSIA has now changed so that it no longer maintains these taxonomies, the baton is being passed on again through a group of interested people and manifested in this key reference work.
Brian Bailey is an independent functional verification consultant helping system designers improve their verification efficiency, and providing guidance and technology services to small start-up companies. He has spent over 20 years creating verification solutions in a number of EDA companies and in recent years has spent most of his time helping the industry understand how and when to adopt new verification methodologies.
Grant Martin is a chief scientist at Tensilica, Inc. in Santa Clara, CA. Prior to Tensilica, Grant worked at Burroughs in Scotland for 6 years, BNR/Nortel in Canada for 10 years, and Cadence for 9 years. His main areas of interest are IP-based design, platform-based design of SoC, and system-level design.
Thomas Anderson is a Director of Technical Marketing at Synopsys, Inc. in Mountain View, CA and chair of the VSIA functional verification working group. Previously he was Vice President of Applications Engineering at 0-In and Vice President of Engineering at Virtual Chips. He has authored over 100 papers and technical articles on verification, IP and interface standards.
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