VLSI-SoC: Forward-Looking Trends in IC and Systems Design
18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers
Erschienen am 24. Februar 2012
X, 358 Seiten
978-3-642-28566-0 (ISBN)
Beschreibung
This book contains extended and revised versions of the best papers presented at the 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, held in Madrid, Spain, in September 2010. The 14 papers included in the book were carefully reviewed and selected from the 52 full papers presented at the conference. The papers cover a wide variety of excellence in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of theses systems.
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Inhalt
- Title Page
- Preface
- Organization
- Table of Contents
- A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole
- Introduction
- Passive Mixer Architectures
- Current-Mode and Voltage-Mode Passive Mixers
- IF Section Pre-filtering
- Voltage-Mode versus Current-Mode Passive Mixers
- The Proposed Architecture
- The Low-Noise Amplifier
- The Passive Mixer
- The Gm-C Filters
- Measurement Results
- Measured Performance
- Comparison
- References
- Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks
- Introduction
- Self-Timed Rings
- Architecture
- Tokens and Bubbles
- Propagation Rules
- Configurability
- Modified Stage
- C-element Implementations
- Designing High-Speed Multiphase Oscillators
- Phase Noise Analysis
- Quadrature Signal Generation
- Frequency Range
- A Design Flow for the Self-Timed Ring Oscillators
- Conclusion
- References
- Adaptive Logical Control of RF LNAPer formances for Efficient Energy Consumption
- Introduction
- Related Works
- Model Building
- Behavioural Input/Output Model
- Nonlinear Performance Prediction Model
- Adaptive Logical Control
- Recursive Parameter Identification
- Logical Control Strategy
- Case Study
- LNA: Low Noise Amplifier
- Envelope Detector
- Variation of Performances with the Power Supply Voltage
- Input Matching and Input Reflection Parameter (S11).
- Gain (S21).
- Noise Figure (NF).
- Non Linearity Effects (1dB Compression).
- Non Linearity Effects (IIP3).
- Isolation Parameter (S12).
- Isolation Parameter (S22).
- LNA Performance Modes
- Simulation Results
- Conclusion
- References
- A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4
- Introduction
- System Specification
- Frequency Synthesis
- Phase Noise
- Spur Rejection
- Settling Time
- Architecture of the Implemented Frequency Synthesizer
- Fully Programmable 1 MHz Resolution Divider
- A TSPC 47/48 Dual-Modulus Prescaler
- A Low Power TSPC 2/3 Prescaler [10]
- Programmable P-Counter
- Swallow S-Counter
- Quadrature Voltage-Controlled Oscillator (QVCO)
- Phase Frequency Detector (PFD) and Charge Pump (CP)
- Loop Filter Design
- Measured Results
- Conclusion
- References
- Design and Optimization of a Digital Baseb and Receiver ASIC for GSM/EDGE
- Introduction
- Outline
- System Overview
- Digital Baseband Receiver
- A Combined Pre-filter and DFSE Solution
- Pre-filter Implementation
- Matrix Inversion
- DFSE Design for GMSK and 8PSK
- Complexity of Combined Pre-filter and DFSE
- Hard-Decision Receiver Back-End Realization
- De-mapping, De-interleaving and De-puncturing
- Flexible Hard-Decision Viterbi Decoder
- Discussion: Hard-Decision vs. Soft-Decision Receiver Back-End
- Implementation Results
- Conclusion
- References
- VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems
- Introduction
- Contributions
- Outline of the Chapter
- Notation
- MIMO System Model and Sphere Decoding
- Wide-Band MIMO System Model
- ML Detection Using the Sphere-Decoding Algorithm
- Sphere-Decoding Algorithm.
- Soft-Output Single Tree-Search Sphere Decoding
- Computation of the Max-Log LLRs.
- Single Tree-Search Sphere Decoding.
- LLR Clipping.
- Wide-Band MIMO Receiver Architecture
- Run-Time Constraints
- Receiver Architecture for Wide-Band MIMO Systems
- Implications on SD-Core Optimization
- VLSI Architecture of Hard-Output SD
- High-Level Architecture
- Schnorr-Euchner Enumeration
- Approximate Schnorr-Euchner Enumeration Schemes
- Pipeline Interleaving
- VLSI Architecture of Soft-Output STS-SD
- Architectural Changes in the MCU
- List Administration and Tree Pruning
- List-Administration Unit (LAU).
- Pruning Criterion Unit (PCU).
- Implementation Results and Comparison
- Implementation Results for Hard-Output SD
- Implementation Results for Soft-Output STS-SD
- The Case for Multiple SD-Cores
- Summary and Conclusion
- References
- Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression
- Introduction
- DCT Optimization Techniques
- Choice of the Algorithm
- Multiplierless DCT Architecture
- Joint Optimization
- Granularity Analysis
- Principle
- Verification
- Validation
- Critical Analysis
- ANewPower-EfficientDCT
- Principle
- New CSE Technique for DCT Algorithm
- Validation for Image Compression
- Image Compression Principle and Simulation
- Design Considerations
- Synthesis Results
- Power Analysis
- Conclusion
- References
- Fast Fixed-Point Optimization of DSP Algorithms
- Introduction
- Related Work
- Fixed-Point Optimization
- Affine Arithmetic
- Description
- Example of Application
- SQNR Estimation
- Affine Arithmetic Applied to Error Propagation Analysis
- Analytical SQNR Estimation
- Accuracy for LTI Systems
- Fixed-Point Optimization Tool
- Estimation-Based Optimization
- Software Implementation
- Results
- Benchmarks
- Experimental Setup
- Accuracy Results
- Computation Time Results
- Conclusions
- References
- Design and Verification of Lazy and Hybrid Implementations of the SELF Protocol
- Introduction
- Contribution
- SELF Overview
- SELF Channel Protocol Verification
- Lazy SELF Control Network Design
- Fork Components
- Eager Fork
- Lazy Fork
- Lazy Join
- Lazy Join Synthesis
- Lazy Join Verification
- Lazy Join Characterization
- Lazy SELF Networks
- Deadlock - D
- Oscillation Due to Logical Instability - LI
- Oscillation Due to Transient Instability - TI
- Hybrid SELF Protocol
- Cycle Cutting
- Runtime Boosting
- Eager to Hybrid Conversion Flow
- MiniMIPS Case Study and Results
- Elasticizing the MiniMIPS
- Eager versus Lazy SELF Implementations
- Eager versus Hybrid SELF Implementations
- Conclusion
- References
- Adaptation Strategies in Multiprocessors System on Chip
- Introduction
- Adaptation Techniques in NoC-Based MPSoCs
- Dynamic Voltage and Frequency Scaling
- Task Migration Support in MPSoC Architecture
- Task Migration Techniques in Purely Distributed MPSoC
- Task Migration Protocols
- Experimental Results
- Task Migration - Closing Remarks
- Memory Organization in MPSoC
- Two Memory Management Philosophies, Implying Two Computation Models
- A Hybrid Memory Model
- Memory Organization - Closing Remarks
- Conclusion
- References
- Tri-mode Operation for Noise Reductionand Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits
- Introduction
- Mode Transition Noise
- Tri-mode MTCMOS Circuits
- Power and Ground Gated Tri-mode MTCMOS
- Tri-mode MTCMOS with Threshold Voltage Tuning
- Low-Leakage Tri-mode MTCMOS Memory Elements
- Sequential Tri-mode MTCMOS Circuits
- Tri-mode MTCMOS Memory Arrays
- Case Study: 32-bit Tri-mode MTCMOS Brent-Kung Adders
- Parker Sizing for Achieving Minimum Noise in Tri-mode MTCMOS Circuits
- Noise Suppression and Parker Size Minimization with Threshold Voltage Tuning
- Characterization of Noise-Aware MTCMOS Techniques
- Chapter Summary
- References
- Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization
- Introduction
- Previous Work
- Our Contribution
- Algorithm
- Binary Index Tree
- Row Scanning
- Obstacle-Aware Cell Ordering
- Cell Insertion
- Find Median
- Experimental Results
- Benchmarks
- HPWL
- Displacement
- Running Time
- Conclusions
- References
- Control Electronic s Integration toward Endoscopic Capsule Robot Performing Legged Locomotion and Illumination
- Introduction
- System Architecture
- Control IC Description
- Technology Selection
- Control IC Architecture
- Implementation Results
- Conclusions
- References
- Smart Camera System-on-Chip Architecture for Real-Time Brush Based Interactive Painting Systems
- Introduction
- Active-Canvas Digital Paint Methods
- Artist-Computer Interfaces for Digital Paint systems
- Virtual Painting with Real-Brushes
- Smart Camera Usage
- Smart Camera SoC Architecture
- Image Processing Pipeline
- Smart Camera SoC Processor Architecture
- Prototype Implementation
- User Experience
- Conclusions and Further Work
- References
- Author Index
