Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Name: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation | 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011, Proceedings
Brand: Springer
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21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011, Proceedings

Jose L. Ayala Braulio Garcia-Camara Manuel Prieto Martino Ruggiero Gilles Sicard(Herausgeber*in)

Springer (Verlag)

Erschienen am 25. September 2011

XI, 352 Seiten

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978-3-642-24154-3 (ISBN)

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Inhalt

Title
Preface
Organization
Table of Contents
A Quick Method for Energy Optimized Gate Sizing of Digital Circuits
Introduction
Energy-Delay Estimation
Delay Model
Energy Model
Circuit Sizing Techniques
Circuit Sizing for Minimum Delay
Circuit Sizing for Minimum Energy
Constant Stage Effort Ratio (CSER) Method
Design Example
Results
Conclusion
References
Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures
Introduction
Related Work
Methodology
Thermal Analysis
Multi-objective Genetic Algorithm
Experimental Setup
Results
Conclusion
References
A System Level Approach to Multi-core Thermal Sensors Calibration
Introduction
Background
System Level Thermal Sensors Calibration
SCC Test Case
Experimental Results
XTS Framework
Sensors Calibration
Hotspot Model Comparison
Conclusions
References
Improving the Robustness of Self-timed SRAM to Variable Vdds
Introduction
Problems in Existing Fully Self-timed SRAM Memory
Proposed New Self-timed SRAM for Robustness
Robustness Improvements by Leakage Reduction
SRAM Bank Realizations and Analysis
Making Use of Memory Deadlocks in Highly Reliable Systems
Conclusions and Future Work
References
Architecture Extensions for Efficient Management of Scratch-Pad Memory
Introduction
Related Work
Architecture Extensions
Hardware Design
Architectural Issues
Experimental Setup
Experimental Results
Conclusions and Future Work
References
Pass Transistor Operation Modeling for Nanoscale Technologies
Introduction
Pass Transistor Structure
Modeling the Pass Transistor Operation
First Region of Operation
Second Region of Operation
Third Region of Operation
Simulation Results
Conclusion
References
Timing Modeling of Flipflops Considering Aging Effects
Introduction
Modeling Basics
General Remarks
Flipflop Modeling
Setup/Hold Skew
Load and Data/Clock Slew
Aging
Conclusion
References
Iterative Timing Analysis Considering Interdependency of Setup and Hold Times
Introduction
Flipflop Modeling
Iterative Timing Analysis
New Problem
Analysis for Constant Clock Period
Determination of Minimal Clock Period
Experimental Results
Comparison of Minimal Clock Period
Runtime
Conclusion
References
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology
Introduction
Technology and Device
Magnetic Tunnel Junction Using Thermally Assisted Switching Method
Technology and Post Process of the Hybrid CMOS/Magnetic Process
Innovative Cell and Tools
4 Transistor Loadless Non-volatile Cell
Full Custom Flow and Tools
Digital Flow and Tools
Conclusion
References
Performance-Driven Clustering of Asynchronous Circuits
Introduction
Background - Performance Metrics
Clustering
Circuit Model
Local Moves
Ensuring Liveness
Maintaining Performance
Implementation
Experimental Results
Summary and Conclusions
References
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing
Introduction
ECG Signal Conditioning Application
Processing Platform Architecture
Single-Core Processor Architecture
Multi-core Processor Architecture
Experimental Results
Conclusion
References
Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores
Introduction
Related Work
Concept of Thermal Management for 3D-Stacked Many-Core Architectures
Thermal Management
Dynamic Communication Virtualization
Thermal Management and Virtualization under Real-Time Constraints
Evaluation Platform and Thermal Evaluation
Conclusion
References
Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks
Introduction
States-of-the-Art
Weather Forecasts
Dynamic Power Management
Experimental Results
Conclusion
References
Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs
Introduction
Scrubbing Xilinx Virtex FPGAs
Internal versus External Scrubbing
Configuration Memory Structure
Readback and Scrubbing Configuration Memory
Self-Reference Scrubber for Inter-FPGA TMR Systems
Inter-FPGA TMR Systems
Scrubber General Description
Simulation Results and Discussion
Conclusions and Future Work
References
Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique
Introduction
CBLPRP Optimization Methodology
Performance Evaluation
Discussion
Conclusion
References
NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode
Introduction
NBTI Model
NBTI Mitigation by Giving Scan-in Vectors
Evaluation of NBTI Mitigation
Experimental Setup
Evaluation Results
Evaluation on Standby Time Ratio
Evaluation on Various Operations
Random Number Generation
Conclusion
References
An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs
Introduction and Previous Works
Process Variation Sensor Structure
Sensor Integration
Design, Simulation and Analysis Results
Conclusion
References
Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution
Introduction
Wilkinson's Method
Generalized Extreme Value Distribution
Conclusion
References
Using Silent Writes in Low-Power Traffic-Aware ECC
Introduction
Related Work
Decoupled EDC and ECC Background
Motivation
TCC
Block Comparison
Methodology
Results
Performance
Cache Access
Energy
Miss Rate
L1 Cache Size and Performance
L1 Cache Size and Total Energy
Conclusion
References
SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging
Introduction
Transistor Aging
Aging Aware Current Source Model
CSM Simulator `SWAT'
Results
Conclusion
References
Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization
Introduction and Related Work
Probabilistic Logic Minimization for a Cost vs Accuracy Tradeoff
Logic Minimization through Bit-Flips in Boolean Function Minterms
Application of Probabilistic Logic Minimization to Datapath Circuits
A General Algorithm for Probabilistic Logic Minimization
Experimental Results and Analysis
Proposed Logic Synthesis Based CAD Flow
Results and Analysis
Conclusion and Future Directions
References
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating
Introduction
Understanding Concurrent CG and PG
CG-PG: Limiting Factors and Design Issues
Proposed Methodology
Problem Statement and Methodology Overview
Sub-Row STI
Proposed Design Flow
Experimental Results
Conclusions and Future Work
References
A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts
Introduction
Related Work
Overview of the PwARCH Framework
A Power Domain Based Methodology
Application To a Case Study
Conclusion and Future Work
References
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits
Introduction
Related Work
Fine-Grained Clock Gating
Low Power Flip-Flops
Preliminary Analysis
Unified Gated Flip-Flop
Unification of Multiple Clock-Gating Circuits
Delay Results
Layout and Area Overhead
Overview of the Test Chip
Power Measurement Results
Evaluation with a Commercial Microprocessor
Experimental Setup
Layout Synthesis Results
Power Consumption Results
Conclusion
References
C-elements for Hardened Self-timed Circuits
Introduction
Self-timed Circuit Structures
C-elements
C-element Simulations
Consequence on C-element Design
Fix Methods
Costs
Trade-off between the Two Methods
Conclusion
References
High-Speed and Low-Power PID Structures for Embedded Applications
Background and Motivation
The Two Most-Used Discrete versions of PID
RMRMA Based PID
Discussion
Conclusion
References
Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits
Introduction
Resonant Clocking
Resonant Clocking for 3-D ICs
Simulation Results
Conclusions
References
Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels
Introduction
Related Work
Opportunities and Challenges of Vertical TSV
BBVC-Based 3D NoC Architecture
Router Architecture
Forecasting-Based Dynamic Frequency Scaling
Experimental Results
Conclusion
References
Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study
Introduction
System Model
Computational Model
Power Model
Thermal Model
Problem Definition
Thermal Analysis
Experimental Analysis
Experimental Setup
Dynamic Frequency Scaling
Thermal-Aware Scheduling
Conclusion
References
A Framework for Architecture-Level Exploration of 3-D FPGA Platforms
Introduction
Motivation
Proposed 3-D FPGA Architecture and Tool Flow
Experimental Results
Conclusion
References
Variability-Speed-Consumption Trade-off in Near Threshold Operation
Introduction
Sub-Threshold Circuit Design
Sub-Threshold Operation
Variability Effect on Subthreshold Circuit
Variability Aware Circuit Model
Current and Delay Model under Variability Analysis
Energy Model under Variability Analysis
Conclusion
References
High Level Synthesis of Asynchronous Circuits from Data Flow Graphs
Introduction
Related Work
Background
Data Flow Graph
Scheduling and Resource Sharing
Bundled-Data
Signal Transition Graphs
De-synchronization
Proposed Method
Toolbox
Datapath
Control Network
Liveness
Handshaking
Handshake Blocks
Results
Conclusion
References
A Secure D Flip-Flop against Side Channel Attacks
Introduction
Cryptographic Devices Leakages
Secure D Flip-Flop
Secure DFF Implementation
Standard Characterisation
Secure Characterisation
Conclusion
References
Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling
Introduction
Related Work
Modeling 3D Systems with Liquid Cooling
3D Heat Propagation Model
Workload Model
Policy Computation
Experimental Setup
3D MPSoC Model
Policy Setup
Experimental Results
Conclusion
References
Author Index

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