Computer Hardware Standards

Source: Wikipedia. Pages: 30. Chapters: RS-232, Musical Instrument Digital Interface, S/PDIF, List of device bit rates, Advanced Configuration and Power Interface, Advanced Computing Environment, OMA Device Management, Intelligent Platform Management Interface, MADI, Open Platform Management Architecture, MPU-401, Host controller interface, SFF-SIG, ETX, SES-2 Enclosure Management, Advanced RISC Computing, COM Express, Qseven, CoreExpress, Unified Power Format, CEA-936-A. Excerpt: This is a list of device bit rates, or physical layer information rates, net bit rates, useful bit rates, peak bit rates or digital bandwidth capacity, at which digital interfaces of computer peripheral equipment and network devices can communicate over various kinds of buses and networks. The distinction can be arbitrary between a bus, which is inside a box and usually relies on many parallel wires, and a communications network cable, which is external, between boxes and rarely relies on more than four wires. Many device interfaces or protocols (e.g. SATA, USB, SCSI, PCI and a few variants of Ethernet) are used both inside many-device boxes, such as a PC, and one-device-boxes, such as a hard drive enclosure. Accordingly, this page lists both the internal ribbon and external communications cable standards together in one sortable table. Most of the listed rates are theoretical maximum throughput measures; in practice, the actual effective throughput is almost inevitably lower in proportion to the load from other devices (network/bus contention), interframe gap, and other overhead in data link layer protocols etc. The maximum goodput¿for example, the file transfer rate¿may be even lower due to higher layer protocol overhead and data packet retransmissions caused by line noise or interference such as crosstalk, or lost packets in congested intermediate network nodes. All protocols lose something, and the more robust ones that deal resiliently with very many failure situations tend to lose more maximum throughput to get higher total long term rates. Device interfaces where one bus transfers data via another will be limited to the throughput of the slowest interface, at best. For instance, SATA 6G controllers on one PCIe 5G channel will be limited to the 5G rate and have to employ more channels to get around this problem. Early implementations of new protocols very often have this kind of problem. The physical phenomena on which the device relies (such as spinning platt