This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management.
Auflage
Softcover reprint of the original 1st ed. 2015
Sprache
Verlagsort
Zielgruppe
Illustrationen
58
132 farbige Abbildungen, 58 s/w Abbildungen
VI, 272 p. 190 illus., 132 illus. in color.
Maße
Höhe: 235 mm
Breite: 155 mm
Dicke: 15 mm
Gewicht
ISBN-13
978-1-4939-4156-8 (9781493941568)
DOI
10.1007/978-1-4614-4078-9
Schweitzer Klassifikation
Introduction.- Recent Trends in Bias Temperature Instability.- Charge trapping phenomena in MOSFETS: From Noise to Bias Temperature Instability.- Atomistic Simulations on Reliability.- On-chip characterization of statistical device degradation.- Circuit Resilience Roadmap.- Layout Aware Electromigration Analysis of Power/Ground Networks.- Power-Gating for Leakage Control and Beyond.- Soft Error Rate and Fault Tolerance Techniques for FPGAs.
