Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits.
Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise.
But the world is not solely digital.
Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market.
Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems.
Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CAD/EDA industry professionals, academics and students.
Auflage
Softcover reprint of the original 1st ed. 1998
Sprache
Verlagsort
Zielgruppe
Für Beruf und Forschung
Research
Illustrationen
Maße
Höhe: 235 mm
Breite: 155 mm
Dicke: 18 mm
Gewicht
ISBN-13
978-1-4613-7545-6 (9781461375456)
DOI
10.1007/978-1-4615-5565-0
Schweitzer Klassifikation
1 Introduction.- 1.1 Focus.- 1.2 Motivation.- 1.3 The Mixed-Signal Design Process.- 1.4 Goals of Analog Design Automation.- 1.5 Research direction.- 1.6 A New Nominal Synthesis Approach.- 1.7 Preview of Nominal Synthesis Results.- 1.8 A New Unified Synthesis Formulation.- 1.9 Preview of Variation-Tolerant Synthesis Results.- 1.10 Book Organization.- 2 Methods for Nominal Analog Circuit Synthesis.- 2.1 Layout-Based Design Automation.- 2.2 Artificial Intelligence Approaches to Design Automation.- 2.3 Simulation-Based Optimization.- 2.4 Equation-Based Synthesis.- 2.5 Comparison of Previous Systems.- 2.6 Where Equation-Based Tools Need to Improve.- 2.7 Summary.- 3 A New Nominal Synthesis Strategy.- 3.1 Goals.- 3.2 Strategy.- 3.3 Architecture.- 3.4 A Design Scenario.- 3.5 Revisiting Unresolved Issues.- 3.6 Summary.- 4 Synthesis Via Annealing.- 4.1 Overview of Simulated Annealing.- 4.2 Problem Representation.- 4.3 Move Generation.- 4.4 Cost function.- 4.5 Annealing Control Mechanisms.- 4.6 Implementation Details.- 4.7 Summary.- 5 A Circuit Compiler.- 5.1 Required Input.- 5.2 Analysis.- 5.3 Code Generation.- 5.4 Implementation.- 5.5 Summary.- 6 Nominal Circuit Synthesis Results.- 6.1 Previously Published Synthesis Results.- 6.2 Device Encapsulation.- 6.3 Design Space Exploration.- 6.4 Comparison with Manual Design.- 6.5 Designing Large, Realistic Cells.- 6.6 Summary.- 7 Validating the Tool Design.- 7.1 Reducing the Need for User-Controlled Constants.- 7.2 The Lam Cooling Schedule.- 7.3 Dynamic Move Selection.- 7.4 Dynamic Weighting.- 7.5 The Relaxed-D.C. Formulation.- 7.6 The Annealing Process: Cost Function Evolution.- 7.7 Summary.- 8 The Second Challenge: Handling Variations.- 8.1 Problems with Variations in Nominal Synthesis.- 8.2 Parametric Yield Maximization.- 8.3 Summary.- 9 A Unified Formulation.- 9.1 Problem Formulation Goals.- 9.2 Strategy.- 9.3 Notation and Formulation.- 9.4 Example.- 9.5 Comparison with Previous Formulations.- 9.6 Summary.- 10 Solving the Infinite Program.- 10.1 Literature Review.- 10.2 Our Solution Approach.- 10.2.4 Sequence of Inner and Outer Optimizations.- 10.3 Local and Global Optimization Methods.- 10.4 Annealing in Annealing Implementation.- 10.5 Synthetic Example.- 10.6 Summary.- 11 Variation-Tolerant Synthesis Results.- 11.1 Simple OTA Circuit.- 11.2 Folded Cascode Amplifier.- 11.3 Manufacturing Line Variations.- 11.4 Band-Gap Reference Circuit.- 11.5 Summary.- 12 Conclusions and Future Work.- 12.1 Introduction.- 12.2 Contributions.- 12.3 Future Work.
