Introduction; T. Nishitani, P.H. Ang, F. Catthoor. VLSI in Picture Coding; T. Ishiguro. Single-Chip Image Sensors with a Digital Processor Array; R. Forchheimer, Keping Chen, C. Svensson, A. Odmark. An Image Processing System using Signal Multiprocessors (ISMPs); H. Nakahira, M. Maruyama, H. Ueda, H. Yamada. A Video-Rate JPEG Chip Set; P.A. Ruetz, Po Tong, D. Luthi, P.H. Ang. DCT/IDCT Processor for HDTV developed with DSP Silicon Compiler; T. Miyazaki, T. Nishitani, M. Edahiro, I. Onon, K. Mitsuhashi. A VLSI Based MIMD Architecture of a Multiprocessor System for Real-Time Video Processing Applications; K. Gaedke, H. Jeschke, P. Pirsch. Design of a Processing Board for a Programmable Multi-VSP System; M. Engels, R. Lauwereins, J.A. Peperstraete, A. van Roermund. A VLSI Neuroprocessor for Image Restoration using Analog Computing-Based Systolic Architecture; Ji-Chen Lee, B.J. Sheu, R. Chellappa. Architectural Strategies for High-Throughput Applications; J. van Meerbergen, P. Lippens, B. McSweeney, W. Verhaegh, A. van der Werf, A. van Zanten. An Application-Specific Architecture for the RBN-Code with Efficient Memory Organization; T. Gijbels, F. Catthoor, L. Van Eycken, A. Oosterlinck, H. De Man. System Considerations and the System Level Design of a Chip Set for Real Time TV and HDTV; C.V. Reventlow, M. Talmi, S. Wolf, M. Ernst, K. Muller, C. Stoffers. Systolic Architectures for Finite-State Vector Quantization; R.K. Kolagotla, Shu-Sun Yu, J.F. JaJa. Parallel Implementation for Iterative Image Restoration Algorithms on a Parallel DSP Machine; R.L. Stevenson, G.B. Adams III, L.H. Jamieson, E.J. Delp. An Optimization Technique for Lowering the Iteration Bound of DSP Programs; F. Buchholz Maciel, Y. Miyanaga, K. Tochinai. Subject Index.
