This book describes the various tradeoffs systems designers face when designing embedded memory. Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test. The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.
Reihe
Auflage
Sprache
Verlagsort
Zielgruppe
Für Beruf und Forschung
Research
Illustrationen
26
37 farbige Abbildungen, 26 s/w Abbildungen
XIII, 95 p. 63 illus., 37 illus. in color.
Maße
Höhe: 241 mm
Breite: 160 mm
Dicke: 12 mm
Gewicht
ISBN-13
978-1-4614-8880-4 (9781461488804)
DOI
10.1007/978-1-4614-8881-1
Schweitzer Klassifikation
Introduction.- Cache Architecture and Main Blocks.- Embedded Memory Hierarchy.- SRAM Memory Operation and Yield.- Low Power and High Yield SRAM Memory.- Leakage Reduction.- Embedded Memory Verification.- Embedded Memory Design Validation and Design For Test.- Emerging Memory Technology Opportunities and Challenges.
