Systolic algorithm design exploits the area at the interface between algorithms and computer architecture. It allows problem structure to determine machine structure, generating algorithmically specialized arrays which employ massive parallelism, high throughput and regular interconnection topologies. This collection of specially commissioned chapters is written by international experts. It draws together the main strands of research in the design of systolic algorithms, explaining the state-of-the-art in formal methods, manipulation methods and design tools. The intention is to provide readers with techniques and methodologies which allow them to adopt a formal approach to the design process. This book should be of interest to graduate students, professionals and researchers working in hardware design in industry and academic institutions.
Reihe
Sprache
Verlagsort
Zielgruppe
Für höhere Schule und Studium
Für Beruf und Forschung
Illustrationen
Maße
Höhe: 234 mm
Breite: 156 mm
ISBN-13
978-0-412-44830-0 (9780412448300)
Copyright in bibliographic data is held by Nielsen Book Services Limited or its licensors: all rights reserved.
Schweitzer Klassifikation
Systematic synthesis of processor arrays from uniform recurrence equations. Topological transformation of systolic systems. Processor-time minimal systolic arrays. Systematic pipelining of processor arrays. Clocks, retimings, and transformations of synchronous concurrent algorithms. Array compiler design for VLSI/WSI systems. DECOMP - a program for mapping DSP algorithms on to systolic arrays. Adapting a sequential algorithm for a systolic design. Experimenting with DTAGS: an interactive transformation system. From architecture to algorithm: a formal approach.