This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
Auflage
Softcover reprint of the original 1st ed. 2014
Sprache
Verlagsort
Zielgruppe
Illustrationen
85
10 farbige Abbildungen, 85 s/w Abbildungen
XIII, 143 p. 95 illus., 10 illus. in color.
Maße
Höhe: 235 mm
Breite: 155 mm
Dicke: 9 mm
Gewicht
ISBN-13
978-1-4939-4817-8 (9781493948178)
DOI
10.1007/978-1-4614-9405-8
Schweitzer Klassifikation
Introduction.- Clock Distribution for fast Networks-on-Chip.- Fast Network-on-Chip Design.- Fast On-Chip Data transfer using Sinusoid Signals.- Conclusion and Future Work.
