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Explains how network processors work and provides detailed information on all major commercial architectures, from features to design considerations
Network processing units (NPUs) will be the occasion of sweeping changes in the network hardware industry over the next few years. This new breed of microchip impacts chip designers like Intel, equipment vendors like Cisco, application developers like IBM and Morotola, and an army of software engineers who spent the last decade working on protocols and network management solutions.A thoroughly practical dissection of the early NPU market, this designer's guide explains how network processors work and provides detailed information on all major commercial architectures, from features to design considerations. Comparative tables are a rich source of cross-industry info. Coverage includes traffic managers, classification chips, content-addressable memories, switch fabrics, security accelerators, storage coprocessors and NetASICs.
Sprache
Verlagsort
Verlagsgruppe
McGraw-Hill Education - Europe
Zielgruppe
Produkt-Hinweis
Fadenheftung
Gewebe-Einband
Illustrationen
Maße
Höhe: 243 mm
Breite: 192 mm
Dicke: 37 mm
Gewicht
ISBN-13
978-0-07-140986-5 (9780071409865)
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Schweitzer Klassifikation
Panos C. Lekkas (Framingham MA) is a 20-year veteran of the communications chip industry, including a stint as the lead architect for IBM's PowerPC. Most recently, as founder and principal of TeleHubLink, he created a family of microchips for network security. Lekkas co-authored the bestselling book Wireless Security, contributing a unique section on hardware issues and solutions.
PART 1: FUNDAMENTALSChapter 1: The Evolution of Network Technology: Distributed Computing and the Convergence of NetworksChapter 2: Network Processors: JustificationChapter 3: Packet ProcessingPART 2: NETWORK PROCESSOR ARCHITECTUREChapter 4: IBM PowerNP(tm)Chapter 5: Intel IXA(tm) Network ProcessorsChapter 6: AMCC nP(tm) Family of Network ProcessorsChapter 7: Agere PayloadPlus(r) Family of Network ProcessorsChapter 8: Motorola's C-Port(tm) Family of Network ProcessorsChapter 9: Other NPU ArchitecturesChapter 10: Alternative Approaches to Network Processing: Net ASICs and Designing with IP CoresPART 3: PERIPHERAL CHIPS SUPPORTING NETWORK PROCESSORS: STORAGE PROCESSORS, CLASSIFICATION PROCESSORS, SEARCH ENGINES, SWITCH FABRICS, AND TRAFFIC MANAGERSChapter 11: Storage Network Processors (SNPs)Chapter 12: Search EnginesChapter 13: Classification ProcessorsChapter 14: Switch FabricsChapter 15: Traffic ManagersPART 4: PUTTING EVERYTHING TOGETHERChapter 16: Systems Engineering IssuesPART 5: SECURITY COPROCESSORSChapter 17: Security CoprocessorsLIST OF ACRONYMSAPPENDIX I: OVERVIEW OF NETWORK-PROCESSOR PRODUCTS AND PLATFORMSAPPENDIX II: TYPICAL TRAFFIC LOAD (in Millions of Packets per Second) CORRESPONDENCE AT VARIOUS LINK SPEEDS AND PACKET SIZESAPPENDIX III: STANDARDIZATION EFFORTS IN NETWORK PROCESSINGINDEX
