In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
Reihe
Auflage
Softcover reprint of the original 1st ed. 1998
Sprache
Verlagsort
Zielgruppe
Für Beruf und Forschung
Research
Illustrationen
Maße
Höhe: 235 mm
Breite: 155 mm
Dicke: 12 mm
Gewicht
ISBN-13
978-1-4613-7561-6 (9781461375616)
DOI
10.1007/978-1-4615-5597-1
Schweitzer Klassifikation
1. Introduction.- 1.1 A Problem of Interest.- 1.2 Overview of the book.- 2. Test Application Schemes for Testing Delay Defects.- 2.1 Combinational Circuits.- 2.2 Sequential Circuits.- 2.3 Testing High Performance Circuits Using Slower Testers.- 2.4 Summary.- 3. Delay Fault Models.- 3.1 Transition Fault Model.- 3.2 Gate Delay Fault Model.- 3.3 Line Delay Fault Model.- 3.4 Path Delay Fault Model.- 3.5 Segment Delay Fault Model.- 3.6 Summary.- 4. Case Studies on Delay Testing.- 4.1 Summary.- 5. Path Delay Fault Classification.- 5.1 Sensitization Criteria.- 5.2 Path Delay Faults that do Not Need Testing.- 5.3 Multiple Path Delay Faults and Primitive Faults.- 5.4 Path Delay Fault Classification for Sequential Circuits.- 5.5 Summary.- 6. Delay Fault Simulation.- 6.1 Transition Fault Simulation.- 6.2 Gate delay fault simulation.- 6.3 Path Delay Fault Simulation.- 6.4 Segment Delay Fault Simulation.- 6.5 Summary.- 7. Test Generation for Path Delay Faults.- 7.1 Robust Tests.- 7.2 High Quality Non-Robust Tests.- 7.3 Validatable Non-Robust Tests.- 7.4 High Quality Functional Sensitizable Tests.- 7.5 Tests for Primitive Faults.- 7.6 Summary.- 8. Design for Delay Fault Testability.- 8.1 Improving The Path Delay Fault Testability by Reducing The Number of Faults.- 8.2 Improving The Path Delay Fault Testability by Increasing Robust Testability of Designs.- 8.3 Improving Path Delay Fault Testability by Increasing Primitive Delay Fault Testability.- 8.4 Summary.- 9. Synthesis for Delay Fault Testability.- 9.1 Synthesis for Robust Delay Fault Testability.- 9.2 Synthesis for Validatable Non-Robust Testable and Delay-Verifiable Circuits.- 9.3 Summary.- 10. Conclusions and Future Work.- References.
