The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability.
Rezensionen / Stimmen
"If Neil Armstrong offers to give you a tour of the lunar module, or Tiger Woods asks you to go play golf with him, you should do it. When Hennessy and Patterson offer to lead you on a tour of where computer architecture is going, they call it Computer Architecture: A Quantitative Approach, 4th Edition. You need one. Tours leave on the hour.? --Robert Colwell, Intel lead designer
"The book has been updated so it covers the latest computer architectures like the 64-bit AMD Opteron as well as those from Sun, Intel and other major vendors ... I highly recommend this book for those learning about computer architecture or those wanting to understand architectures that differ from those they are currently using. It does an excellent job of covering most of the major architectural approaches employed today.? --William Wong, Electronic Design, November 2006
"Computer hardware is entering into a new era, what with multicore processing, virtualization and other enhancements ... Computer Architecture covers these topics and updates the insightful work in the earlier editions that laid out the full range of metrics needed for evaluating processor performance.? --Joab Jackson, GCN, November 20, 2006
Reihe
Auflage
Sprache
Verlagsort
Verlagsgruppe
Elsevier Science & Technology
Zielgruppe
Für höhere Schule und Studium
Editions-Typ
Maße
Höhe: 235 mm
Breite: 191 mm
Gewicht
ISBN-13
978-0-12-370490-0 (9780123704900)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Klassifikation
ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates. David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1977.His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Prof. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Prof. Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.
Autor*in
Departments of Electrical Engineering and Computer Science, Stanford University, USA
Pardee Professor of Computer Science, Emeritus, University of California at Berkeley, USA
Main Text
Chapter 1: Fundamentals of Computer Design
Chapter 2: Instruction-level Parallelism and its Exploitation
Chapter 3: Advanced Techniques for Exploiting Instruction-level Parallelism and their Limits
Chapter 4: Multiprocessors and Thread-level Parallelism
Chapter 5: Memory Hierarchy Design
Chapter 6: Storage Systems
Appendix A: Pipelining: Basic and Intermediate
Concepts
Appendix B: Instruction Set Principles and Examples
Appendix C: Introduction to Memory Hierarchy
CD
Appendix D: Embedded Systems (contributor: Thomas M. Conte, North Carolina State University)
Appendix E: Interconnection Networks (contributor: Timothy M. Pinkston, USC and Jose Duato, Simula)
Appendix F: Vector Processors (contributor: Krste Asanovic, MIT)
Appendix G: Hardware and Software for VLIW and EPIC
Appendix H: Large-Scale Multiprocessors and Scientific Apps
Appendix I: Computer Arithmetic (contributor: David Goldberg, Xerox PARC)
Appendix J: Survey of Instruction Set Architectures
Appendix K: Historical Perspectives with References
