Part 1 Logic synthesis: new directions in logic synthesis, R.K. Brayton; Hewlett-Packard logic synthesis, B. Culbertson and B. Shackleford; logic synthesis expert system using a structured knowledge representation, N. Matsumoto and T. Nishiyama; lexicographical expression of Boolean function for multilevel synthesis of high speed circuits, P. Abouzeid et al; extraction of arithmetic functions expressible by polynomial-size binary decision diagrams, N. Ishiura and S. Yajima; the role of don't care co-ordination in synchronous logic optimization, M. Damiani and G. De Micheli. Part 2 Synthesis from high-level descriptions: CAD for real-time information processing systems - challenges and opportunities, H. de Man; a simple single-block implementation and efficient state-assignments for statecharts, D. Drusinsky-Yoresh; control logic synthesis method based on local behaviour analysis, R. Kuroda et al; a study on the application specific microprocessor design environment, J. Salo and M. Imai; controller state assignment for optimal global area implementation, G. Saucier and C. Duff; optimized synthesis of large controllers on a ROM based architecture, L. Gerbaux and G. Saucier; automata-theoretic aids to scheduling, W. Wolf. Part 3 Rump session: high-level synthesis, R.W. Dutton. Part 4 Simulation and verification: formal hardware verification by symbolic simulation, R.E. Bryant; timing models for compiler driven logic simulation, W. Hahn et al; behaviour level simulation of mixed level simulator melon 2, M. Mozuno et al; coded time-symbolic simulation - simulation of logic circuits with nondeterministic delays based on Boolean function manipulation, Y. Deguchi et al; fault simulation for multiple faults using shared binary decision diagrams, N. Takahashi et al; semantic gap between hardware design languages and simulators, H. Yasuura et al; vector processor design using an hierarchical behavioural based CAD system, H. Ohta et al; a software development system for digital signal processors based on a knowledge-based optimizing compiler and a digital processing language, A. Hirano et al; CAD tools for digital filter design, K. Ikeda et al; CAD system for an application-specific DSP processor design, L.G. Chen et al; pipeline interleaving design for FIR, IIR, and FFT, I.G. Chen et al; matching method for concurrent operatorm register and multiplexer allocation, A. Mignotte and G. Saucier. (part contents).
