Using Machine-Learning to Efficiently Explore the Architecture/Compiler Co-Design Space

Designing new microprocessors is a time-consuming task. Architects rely on slow simulators to evaluate performance and a significant proportion of the design space has to be explored before an implementation is chosen. This becomes even more time-consuming when compiler optimisations are considered as part of the design process; once a new architecture is selected, a new compiler must be developed and tuned.

This thesis proposes the use of machine-learning to address architecture/compiler co-design. The techniques developed in this work represent a new methodology that has the potential to speed up the design of new processors and automate the generation of the corresponding optimising compilers, resulting in higher system efficiency and shorter time-to-market.