Architecture and Hardware Support for AI Processing: VLSI Design of a 3D Highly Parallel MessagePassing Architecture (J.L. Bechennec et al.). Architectural Design of the Rewrite Rule Machine Ensemble (H. Aida et al.). A Dataflow Architecture for AI (J. DelgadoFrias et al.). Machines for Prolog: An Extended Prolog Instruction Set for RISC Processors (A. Krall). A VLSI Engine for Structured Logic Programming (P. Civera et al.). Performance Evaluation of a VLSI Associative Unifier in a WAM Based Environment (P. Civera et al.). Analogue and Pulse Stream Neural Networks: Computational Capabilities of BiologicallyRealistic Analog Processing Elements (C. Fields et al.). Analog VLSI Models of Mean Field Networks (C. Schneider et al.). An Analogue Neuron Suitable for a Data Frame Architecture (W.A.J. Waller et al.). Digital Implementations of Neural Networks: The VLSI Implementation of the sigma Architecture (S.R. Williams et al.). A Cascadable VLSI Architecture for the Realization of Large Binary Associative Networks (W. Poechmueller et al.). Digital VLSI Implementations of an Associative memory Based on Neural Networks (U. Rückert). Arrays for Neural Networks: A Highly Parallel Digital Architecture for Neural Network Emulation (D. Hammerstrom). 26 additional articles. Index.
Auflage
Sprache
Verlagsort
Verlagsgruppe
Kluwer Academic Publishers Group
Zielgruppe
Für höhere Schule und Studium
Für Beruf und Forschung
Research
Produkt-Hinweis
Fadenheftung
Gewebe-Einband
Illustrationen
Maße
Höhe: 250 mm
Breite: 175 mm
Dicke: 29 mm
Gewicht
ISBN-13
978-0-306-44029-8 (9780306440298)
DOI
10.1007/978-1-4615-3752-6
Schweitzer Klassifikation
Architecture and Hardware Support for AI Processing: VLSI Design of a 3D Highly Parallel MessagePassing Architecture (J.L. Bechennec et al.). Architectural Design of the Rewrite Rule Machine Ensemble (H. Aida et al.). A Dataflow Architecture for AI (J. DelgadoFrias et al.). Machines for Prolog: An Extended Prolog Instruction Set for RISC Processors (A. Krall). A VLSI Engine for Structured Logic Programming (P. Civera et al.). Performance Evaluation of a VLSI Associative Unifier in a WAM Based Environment (P. Civera et al.). Analogue and Pulse Stream Neural Networks: Computational Capabilities of BiologicallyRealistic Analog Processing Elements (C. Fields et al.). Analog VLSI Models of Mean Field Networks (C. Schneider et al.). An Analogue Neuron Suitable for a Data Frame Architecture (W.A.J. Waller et al.). Digital Implementations of Neural Networks: The VLSI Implementation of the sigma Architecture (S.R. Williams et al.). A Cascadable VLSI Architecture for the Realization of Large Binary Associative Networks (W. Poechmueller et al.). Digital VLSI Implementations of an Associative memory Based on Neural Networks (U. Rückert). Arrays for Neural Networks: A Highly Parallel Digital Architecture for Neural Network Emulation (D. Hammerstrom). 26 additional articles. Index.
