TheSAMOSworkshopisaninternationalgatheringofhighlyquali?edresearchers from academia and industry, sharing ideas in a 3-day lively discussion on the quietandinspiringnorthernmountainsideoftheMediterraneanislandofSamos. The workshopmeeting is one of two co-locatedevents (the other event being the IC-SAMOS).Asatradition,theworkshopfeaturespresentationsinthemorning, while after lunch all kinds of informal discussions and nut-cracking gatherings take place. The workshop is unique in the sense that not only solved research problems are presented and discussed but also (partly) unsolved problems and in-depth topical reviews can be unleashed in the scienti?c arena. Consequently, the workshopprovidesthe participantswithanenvironmentwherecollaboration rather than competition is fostered. The SAMOS conference and workshop were established in 2001 by Stamatis Vassiliadis with the goals outlined above in mind, and located on Samos, one of the most beautiful islands of the Aegean.
The rich historical and cultural environment of the island, coupled with the intimate atmosphereandthe slowpaceofasmallvillagebythe seainthe middle of the Greek summer, provide a very conducive environment where ideas can be exchanged and shared freely.
Reihe
Auflage
Sprache
Verlagsort
Verlagsgruppe
Zielgruppe
Für Beruf und Forschung
Research
Illustrationen
Maße
Höhe: 235 mm
Breite: 155 mm
Dicke: 20 mm
Gewicht
ISBN-13
978-3-642-03137-3 (9783642031373)
DOI
10.1007/978-3-642-03138-0
Schweitzer Klassifikation
Beachnote.- What Else Is Broken? Can We Fix It?.- Architectures for Multimedia.- Programmable and Scalable Architecture for Graphics Processing Units.- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors.- CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.- Programmable Accelerators for Reconfigurable Video Decoder.- Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study.- Multiple Description Scalable Coding for Video Transmission over Unreliable Networks.- Multi/Many Cores Architectures.- Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC.- Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture.- Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management.- A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA.- VLSI Architectures Design.- Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing.- Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata.- Prediction in Dynamic SDRAM Controller Policies.- Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI.- Architecture Modeling and Exploration Tools.- Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration.- Modeling Scalable SIMD DSPs in LISA.- NoGAP: A Micro Architecture Construction Framework.- A Comparison of NoTA and GENESYS.- Special Session 1: Instruction-Set Customization.- to Instruction-Set Customization.- Constraint-Driven Identification of Application Specific Instructions in the DURASE System.- A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs).- Runtime Adaptive Extensible Embedded Processors - A Survey.- Special Session 2: The Future of Reconfigurable Computing and Processor Architectures.- to the Future of Reconfigurable Computing and Processor Architectures.- An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems.- Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study.- Reconfigurable Multicore Server Processors for Low Power Operation.- Reconfigurable Computing in the New Age of Parallelism.- Reconfigurable Multithreading Architectures: A Survey.- Special Session 3: Mastering Cell BE and GPU Execution Platforms.- to Mastering Cell BE and GPU Execution Platforms.- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.- Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs.- Experiences with Cell-BE and GPU for Tomography.- Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell.- Exploiting Locality on the Cell/B.E. through Bypassing.- Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System.
