This book constitutes the refereed proceedings of the 14th International Conference on Field-Programmable Logic, FPL 2003, held in Leuven, Belgium in August/September 2004. The 78 revised full papers, 45 revised short papers, and 29 poster abstracts presented together with 3 keynote contributions and 3 tutorial summaries were carefully reviewed and selected from 285 papers submitted. The papers are organized in topical sections on organic and biologic computing, security and cryptography, platform-based design, algorithms and architectures, acceleration application, architecture, physical design, arithmetic, multitasking, circuit technology, network processing, testing, applications, signal processing, computational models and compiler, dynamic reconfiguration, networks and optimisation algorithms, system-on-chip, high-speed design, image processing, network-on-chip, power-aware design, IP-based design, co-processing architectures, system level design, physical interconnect, computational models, cryptography and compression, network applications and architecture, and debugging and test.
Reihe
Auflage
Sprache
Verlagsort
Verlagsgruppe
Zielgruppe
Für höhere Schule und Studium
Research
Illustrationen
Maße
Höhe: 23.5 cm
Breite: 15.5 cm
Gewicht
ISBN-13
978-3-540-22989-6 (9783540229896)
DOI
Schweitzer Klassifikation
Plenary Keynotes.- Organic and Biology Computing.- Security and Cryptography 1.- Platform Based Design.- Algorithms and Architectures.- Acceleration Application 1.- Architecture 1.- Physical Design 1.- Arithmetic 1.- Multitasking.- Circuit Technology.- Memory 1.- Network Processing.- Testing.- Applications.- Arithmetic 2.- Signal Processing 1.- Computational Models and Compiler.- Dynamic Reconfiguration 1.- Network and Optimization Algorithms.- System-on-Chip 1.- High Speed Design.- Security and Cryptography 2.- Architectures 2.- Memory 2.- Image Processing 1.- Network-on-Chip.- Power Aware Design 1.- IP-Based Design.- Power Aware Design 2.- Coprocessing Architectures.- Embedded Tutorials.- Dynamic Reconfiguration 2.- Physical Design 2.- Acceleration Application 2.- System Level Design.- Physical Interconnect.- Computational Models.- Acceleration Applications 3.- Arithmetic 3.- Signal Processing 2.- System-on-Chip 2.- Image Processing 2.- Cryptography and Compression.- Network Applications and Architectures.- Network on Chip and Adaptive Architectures.- Debugging and Test.- Organic and Biology Computing (Poster).- Security and Cryptography (Poster).- Mapping and Compilers (Poster).- Architectures (Poster).- Algorithms and IP (Poster).- Image Processing (Poster).- PhD Forum (Poster).
