System-on-Chip for Real-Time Applications will be of interest to engineers, both in industry and academia, working in the area of SoC VLSI design and application. It will also be useful to graduate and undergraduate students in electrical and computer engineering and computer science.
A selected set of papers from the 2nd International Workshop on Real-Time Applications were used to form the basis of this book. It is organized into the following chapters:
-Introduction;
-Design Reuse;
-Modeling;
-Architecture;
-Design Techniques;
-Memory;
-Circuits;
-Low Power;
-Interconnect and Technology;
-MEMS.
System-on-Chip for Real-Time Applications contains many signal processing applications and will be of particular interest to those working in that community.
Reihe
Auflage
Softcover reprint of the original 1st ed. 2003
Sprache
Verlagsort
Zielgruppe
Für Beruf und Forschung
Research
Illustrationen
Maße
Höhe: 235 mm
Breite: 155 mm
Dicke: 26 mm
Gewicht
ISBN-13
978-1-4613-5034-7 (9781461350347)
DOI
10.1007/978-1-4615-0351-4
Schweitzer Klassifikation
System on Chip: The Challenge and Opportunities.- Electronic Product Innovation Direct Mapped Signal Processing SoC Cores.- System-On-Chip Implementation Of Signal Processors.- Methodologies and Strategies for Effective Design-Reuse.- A VHDL/SystemC Comparison in Handling Design Reuse.- Aspect Partitioning for Hardware Verification Reuse.- Reconfigurable Combinatorial Accelerators for Real Time Processing.- Tuning Methodologies for Parameterized Systems Design.- Formal Verifications of Systems on Chips: Current and Future Directions.- A Practical Approach to the Formal Verification of SoC's with Symbolic Model-Checking.- High Performance Verification Solutions for SOC Designs.- Novel Test Methodologies for SoC/IP Design: Implementation and Comparison.- SOC Modeling and Simulation Based on Java.- RTOS Modeling Using SystemC.- Modeling, Synthesis and Implementation of Communicating Hierarchical FSM.- A Modeling Method for Reconfigurable Architectures.- The Syslib-Picasso Methodology for the Co-Design Specification Capture Phrase.- Automatic Porting Of Binary File Descriptor Library.- Code Compression on Transport Triggered Architectures.- An Approach To Flexible Multi-Level Network Design.- Survey of Emerging Nonvolatile Embedded Memory Technologies.- Configurable Parallel Memory Implementation For System-on-Chip Designs.- XOR-scheme Implementations In Configurable Parallel Memory.- An Novel Low Power Embedded Memory Architecture for MPEG-4 Applications with Mobile Devices.- Assessment of MPEG-4 VTC and JPEG2000 Dynamic Memory Requirements.- Modified Distributed Arithmetic Architecture for Adiabatic DSP Systems.- Design of a CMOS Wide Range Logarithmic Amplifier with a Modified Parallel Architecture.- Digital Hardware Implementation of Continuous & Discrete ChaoticGenerators.- Novel 1-Bit Full Adder Cells For Low-Power System-On-Chip Applications.- A New Logic Method for considering Low Power and High Testibility.- System Synthesis for Optically-Connected, Multiprocessors On-chip.- Low Power System On Chip Platform Architecture for High Performance Applications.- SOC Interconnect in Deep Submicron.- Optimizing Inductive Interconnect for Low Power.- Skin Effects in System on a Chip Interconnects.- Road Map Towards Designing MEMS Devices with High-Reliability.- A Mems Socket Interface For Soc Connectivity.- On the Application of Finite Element to Investigate the Reliability of Electrostatic Comb-Drive Actuators Utilized in Micro-Fluidic and Space Systems.- An HDL Model For A Vacuum-Sealed Micromachined Pressure Sensor.- Performance Analysis of MEMS-based Inertial Sensors for Positioning Applications.
