Analysis and Design of Analog Integrated Circuits
Beschreibung
Authoritative and comprehensive textbook on the fundamentals of analog integrated circuits, with learning aids included throughout
Written in an accessible style to ensure complex content can be appreciated by both students and professionals, this Sixth Edition of Analysis and Design of Analog Integrated Circuits is a highly comprehensive textbook on analog design, offering in-depth coverage of the fundamentals of circuits in a single volume. To aid in reader comprehension and retention, supplementary material includes end of chapter problems, plus a Solution Manual for instructors.
In addition to the well-established concepts, this Sixth Edition introduces a new super-source follower circuit and its large-signal behavior, frequency response, stability, and noise properties. New material also introduces replica biasing, describes and analyzes two op amps with replica biasing, and provides coverage of weighted zero-value time constants as a method to estimate the location of dominant zeros, pole-zero doublets (including their effect on settling time and three examples of circuits that create doublets), the effect of feedback on pole-zero doublets, and MOS transistor noise performance (including a thorough treatment on thermally induced gate noise).
Providing complete coverage of the subject, Analysis and Design of Analog Integrated Circuits serves as a valuable reference for readers from many different types of backgrounds, including senior undergraduates and first-year graduate students in electrical and computer engineering, along with analog integrated-circuit designers.
Weitere Details
Weitere Ausgaben
Andere Ausgaben
Personen
Paul R. Gray, Professor Emeritus, Executive Vice Chancellor and Provost Emeritus, UC Berkeley, CA, USA. Gray joined the faculty of the Department of Electrical Engineering and Computer Sciences at U.C. Berkeley in 1971. His research interests have included bipolar and MOS circuit design, electro-thermal interactions in integrated circuits, device modeling, telecommunications circuits, and analog-digital interfaces in VLSI systems. He is a Fellow of the IEEE.
Paul J. Hurst, Professor, UC Davis, CA, USA. Hurst received his Ph.D. in Electrical Engineering from the University of California, Berkeley, in 1983. His research interests are in analog and mixed-signal integrated circuit design for analog-digital interfaces and digital communications using CMOS technologies.
Stephen H. Lewis, Professor, UC Davis, CA, USA. Lewis received his PhD degree from the University of California, Berkeley, in 1987. His interests include circuit design for data-conversion and signal-processing systems.
Robert G. Meyer, Professor Emeritus, UC Berkeley, CA, USA. Meyer has enjoyed a distinguished career in both academia and industry since joining UCB in 1968. In 2014, he received the IEEE Donald O. Pederson Award for pioneering contributions to the design and modeling of analog and radio-frequency circuits. He holds eight U.S. patents and is a Fellow of the IEEE.
Inhalt
Chapter 1 Models for Integrated-Circuit Active Devices 1
1.1 Introduction 1
1.2 Depletion Region of a pn Junction 1
1.2.1 Depletion-Region Capacitance 5
1.2.2 Junction Breakdown 7
1.3 Large-Signal Behavior of Bipolar Transistors 9
1.3.1 Large-Signal Models in the Forward-Active Region 9
1.3.2 Effects of Collector Voltage on Large-Signal Characteristics in the Forward-Active Region 14
1.3.3 Saturation and Inverse-Active Regions 16
1.3.4 Transistor Breakdown Voltages 21
1.3.5 Dependence of Transistor Current Gain ß F on Operating Conditions 24
1.4 Small-Signal Models of Bipolar Transistors 26
1.4.1 Transconductance 26
1.4.2 Base-Charging Capacitance 28
1.4.3 Input Resistance 29
1.4.4 Output Resistance 30
1.4.5 Basic Small-Signal Model of the Bipolar Transistor 30
1.4.6 Collector-Base Resistance 31
1.4.7 Parasitic Elements in the Small-Signal Model 31
1.4.8 Specification of Transistor Frequency Response 35
1.5 Large-Signal Behavior of Metal-Oxide-Semiconductor Field-Effect Transistors 39
1.5.1 Transfer Characteristics of MOS Devices 39
1.5.2 Comparison of Operating Regions of Bipolar and MOS Transistors 46
1.5.3 Decomposition of Gate-Source Voltage 48
1.5.4 Threshold Temperature Dependence 48
1.5.5 MOS Device Voltage Limitations 49
1.6 Small-Signal Models of MOS Transistors 50
1.6.1 Transconductance 51
1.6.2 Intrinsic Gate-Source and Gate-Drain Capacitance 52
1.6.3 Input Resistance 53
1.6.4 Output Resistance 53
1.6.5 Basic Small-Signal Model of the MOS Transistor 53
1.6.6 Body Transconductance 54
1.6.7 Parasitic Elements in the Small-Signal Model 55
1.6.8 MOS Transistor Frequency Response 57
1.7 Short-Channel Effects in MOS Transistors 60
1.7.1 Velocity Saturation from the Horizontal Field 60
1.7.2 Transconductance and Transition Frequency 64
1.7.3 Mobility Degradation from the Vertical Field 66
1.8 Weak Inversion in MOS Transistors 67
1.8.1 Drain Current in Weak Inversion 67
1.8.2 Transconductance and Transition Frequency in Weak Inversion 70
1.9 Substrate Current Flow in MOS Transistors 73
A.1.1 Summary of Active-Device Parameters 74
Problems 76
References 78
General References 79
Chapter 2 Bipolar, MOS, and BiCMOS Integrated-Circuit Technology 81
2.1 Introduction 81
2.2 Basic Processes in Integrated-Circuit Fabrication 82
2.2.1 Electrical Resistivity of Silicon 82
2.2.2 Solid-State Diffusion 83
2.2.3 Electrical Properties of Diffused Layers 85
2.2.4 Photolithography 87
2.2.5 Epitaxial Growth 89
2.2.6 Ion Implantation 90
2.2.7 Local Oxidation 90
2.2.8 Polysilicon Deposition 90
2.3 High-Voltage Bipolar Integrated-Circuit Fabrication 91
2.4 Advanced Bipolar Integrated-Circuit Fabrication 95
2.5 Active Devices in Bipolar Analog Integrated Circuits 98
2.5.1 Integrated-Circuit npn Transistors 99
2.5.2 Integrated-Circuit pnp Transistors 111
2.6 Passive Components in Bipolar Integrated Circuits 118
2.6.1 Diffused Resistors 119
2.6.2 Epitaxial and Epitaxial-Pinch Resistors 122
2.6.3 Integrated-Circuit Capacitors 124
2.6.4 Zener Diodes 124
2.6.5 Junction Diodes 125
2.7 Modifications to the Basic Bipolar Process 127
2.7.1 Dielectric Isolation 127
2.7.2 Compatible Processing for High-Performance Active Devices 128
2.7.3 High-Performance Passive Components 131
2.8 MOS Integrated-Circuit Fabrication 131
2.9 Active Devices in MOS Integrated Circuits 135
2.9.1 n-Channel Transistors 135
2.9.2 p-Channel Transistors 148
2.9.3 Depletion Devices 148
2.9.4 Bipolar Transistors 149
2.10 Passive Components in MOS Technology 150
2.10.1 Resistors 150
2.10.2 Capacitors in MOS Technology 152
2.10.3 Latchup in CMOS Technology 155
2.11 BiCMOS Technology 156
2.12 Heterojunction Bipolar Transistors 157
2.13 Interconnect Delay 160
2.14 Economics of Integrated-Circuit Fabrication 160
2.14.1 Yield Considerations in Integrated-Circuit Fabrication 161
2.14.2 Cost Considerations in Integrated-Circuit Fabrication 163
A.2.1 Spice Model-Parameter Files 166
Problems 167
References 170
Chapter 3 Single-Transistor and Multiple-Transistor Amplifiers 173
3.1 Device Model Selection for Approximate Analysis of Analog Circuits 174
3.2 Two-Port Modeling of Amplifiers 175
3.3 Basic Single-Transistor Amplifier Stages 177
3.3.1 Common-Emitter Configuration 178
3.3.2 Common-Source Configuration 182
3.3.3 Common-Base Configuration 186
3.3.4 Common-Gate Configuration 189
3.3.5 Common-Base and Common-Gate Configurations with Finite r o 191
3.3.6 Common-Collector Configuration (Emitter Follower) 195
3.3.7 Common-Drain Configuration (Source Follower) 198
3.3.8 Common-Emitter Amplifier with Emitter Degeneration 201
3.3.9 Common-Source Amplifier with Source Degeneration 204
3.4 Multiple-Transistor Amplifier Stages 206
3.4.1 The CC-CE, CC-CC, and Darlington Configurations 206
3.4.2 The Cascode Configuration 210
3.4.3 The Active Cascode 214
3.4.4 The Super Source Follower 216
3.5 Differential Pairs 219
3.5.1 The dc Transfer Characteristic of an Emitter-Coupled Pair 219
3.5.2 The dc Transfer Characteristic with Emitter Degeneration 221
3.5.3 The dc Transfer Characteristic of a Source-Coupled Pair 222
3.5.4 Introduction to the Small-Signal Analysis of Differential Amplifiers 225
3.5.5 Small-Signal Characteristics of Balanced Differential Amplifiers 228
3.5.6 Device Mismatch Effects in Differential Amplifiers 235
A.3.1 Elementary Statistics and the Gaussian Distribution 250
Problems 253
References 257
Chapter 4 Current Mirrors, Active Loads, and References 259
4.1 Introduction 259
4.2 Replica Biasing 259
4.3 Current Mirrors 261
4.3.1 General Properties 261
4.3.2 Simple Current Mirror 263
4.3.3 Simple Current Mirror with Beta Helper 269
4.3.4 Simple Current Mirror with Degeneration 270
4.3.5 Cascode Current Mirror 272
4.3.6 Wilson Current Mirror 283
4.4 Active Loads 287
4.4.1 Motivation 287
4.4.2 Common-Emitter-Common-Source Amplifier with Complementary Load 288
4.4.3 Common-Emitter-Common-Source Amplifier with Depletion Load 291
4.4.4 Common-Emitter-Common-Source Amplifier with Diode-Connected Load 293
4.4.5 Differential Pair with Current-Mirror Load 296
4.5 Voltage and Current References 309
4.5.1 Low-Current Biasing 309
4.5.2 Supply-Insensitive Biasing 315
4.5.3 Temperature-Insensitive Biasing 327
A.4.1 Matching Considerations in Current Mirrors 338
A.4.1.1 Bipolar 338
A.4.1.2 Mos 340
A.4.2 Input Offset Voltage of a Differential Pair with Active Load 343
A.4.2.1 Bipolar 343
A.4.2.2 Mos 345
Problems 348
References 353
Chapter 5 Output Stages 355
5.1 Introduction 355
5.2 The Emitter Follower as an Output Stage 355
5.2.1 Transfer Characteristics of the Emitter-Follower 356
5.2.2 Power Output and Efficiency 359
5.2.3 Emitter-Follower Drive Requirements 366
5.2.4 Small-Signal Properties of the Emitter Follower 366
5.3 The Source Follower as an Output Stage 368
5.3.1 Transfer Characteristics of the Source Follower 368
5.3.2 Distortion in the Source Follower 370
5.3.3 Transfer Characteristics of the Super Source Follower 374
5.4 Class B Push-Pull Output Stage 378
5.4.1 Transfer Characteristic of the Class B Stage 378
5.4.2 Power Output and Efficiency of the Class B Stage 381
5.4.3 Practical Realizations of Class B Complementary Output Stages 385
5.4.4 All-npn Class B Output Stage 392
5.4.5 Quasi-Complementary Output Stages 394
5.4.6 Overload Protection 397
5.5 CMOS Class AB Output Stages 399
5.5.1 Common-Drain Configuration 399
5.5.2 Common-Source Configuration with Error Amplifiers 401
5.5.3 Alternative Configurations 408
Problems 415
References 420
Chapter 6 Operational Amplifiers with Single-Ended Outputs 421
6.1 Applications of Operational Amplifiers 422
6.1.1 Basic Feedback Concepts 422
6.1.2 Inverting Amplifier 423
6.1.3 Noninverting Amplifier 425
6.1.4 Differential Amplifier 425
6.1.5 Nonlinear Analog Operations 426
6.1.6 Integrator, Differentiator 427
6.1.7 Internal Amplifiers 428
6.2 Deviations from Ideality in Real Operational Amplifiers 436
6.2.1 Input Bias Current 437
6.2.2 Input Offset Current 437
6.2.3 Input Offset Voltage 438
6.2.4 Common-Mode Input Range 438
6.2.5 Common-Mode Rejection Ratio (cmrr) 439
6.2.6 Power-Supply Rejection Ratio (psrr) 440
6.2.7 Input Resistance 441
6.2.8 Output Resistance 442
6.2.9 Frequency Response 442
6.2.10 Operational-Amplifier Equivalent Circuit 442
6.3 Basic Two-Stage MOS Operational Amplifiers 443
6.3.1 Input Resistance, Output Resistance, and Open-Circuit Voltage Gain 444
6.3.2 Output Swing 446
6.3.3 Input Offset Voltage 446
6.3.4 Common-Mode Rejection Ratio 450
6.3.5 Common-Mode Input Range 451
6.3.6 Power-Supply Rejection Ratio (psrr) 453
6.3.7 Effect of Overdrive Voltages 458
6.3.8 Layout Considerations 459
6.3.9 Amplifier with Level Shifting in the Input Stage 462
6.4 Two-Stage MOS Operational Amplifiers with Cascodes 465
6.5 MOS Folded-Cascode Operational Amplifiers 467
6.6 MOS Telescopic-Cascode Operational Amplifiers 471
6.7 Replica Biasing of the Tail Current Source 475
6.8 MOS Active-Cascode Operational Amplifiers 489
Problems 492
References 498
Chapter 7 Frequency Response of Integrated Circuits 499
7.1 Introduction 499
7.2 Single-Stage Amplifiers 499
7.2.1 Single-Stage Voltage Amplifiers and the Miller Effect 499
7.2.2 Frequency Response of the Common-Mode Gain for a Differential Amplifier 511
7.2.3 Frequency Response of Voltage Buffers 513
7.2.4 Frequency Response of Current Buffers 527
7.3 Multistage Amplifier Frequency Response 531
7.3.1 Dominant-Pole Approximation 531
7.3.2 Zero-Value Time Constant Analysis 532
7.3.3 Cascade Voltage-Amplifier Frequency Response 537
7.3.4 Cascode Frequency Response 541
7.3.5 Frequency Response of a Current Mirror Loading a Differential Pair 548
7.3.6 Short-Circuit Time Constants 549
7.3.7 Weighted Zero-Value Time Constants 554
7.4 Relation Between Frequency Response and Time Response 563
7.5 Pole-Zero Doublets 565
7.5.1 Effect of a Pole-Zero Doublet on Settling Time 565
7.5.2 Frequency Dependence of a Cascode Current-Source Load 570
7.5.3 Frequency Dependence of an Active-Cascode Current-Source Load 572
7.5.4 Doublet in a Differential Amplifier with Mismatch 574
Problems 575
References 584
Chapter 8 Feedback 585
8.1 Ideal Feedback Equation 585
8.2 Gain Sensitivity 587
8.3 Effect of Negative Feedback on Distortion 587
8.4 Feedback Configurations 589
8.4.1 Series-Shunt Feedback 589
8.4.2 Shunt-Shunt Feedback 592
8.4.3 Shunt-Series Feedback 594
8.4.4 Series-Series Feedback 595
8.5 Practical Configurations and the Effect of Loading 595
8.5.1 Shunt-Shunt Feedback 596
8.5.2 Series-Series Feedback 602
8.5.3 Series-Shunt Feedback 611
8.5.4 Shunt-Series Feedback 617
8.5.5 Summary 620
8.6 Single-Stage Feedback 620
8.6.1 Local Series-Series Feedback 622
8.6.2 Local Series-Shunt Feedback 624
8.7 The Voltage Regulator as a Feedback Circuit 626
8.8 Feedback Circuit Analysis Using the Return Ratio 632
8.8.1 Closed-Loop Gain Using the Return Ratio 634
8.8.2 Closed-Loop Impedance Formula Using the Return Ratio 640
8.8.3 Summary-Return-Ratio Analysis 646
8.9 Modeling Input and Output Ports in Feedback Circuits 646
Problems 649
References 656
Chapter 9 Frequency Response and Stability of Feedback Amplifiers 657
9.1 Introduction 657
9.2 Relation Between Gain and Bandwidth in Feedback Amplifiers 657
9.3 Instability 659
9.3.1 The Nyquist Criterion 659
9.3.2 Phase Margin and Gain Margin 661
9.3.3 Stability of the Super Source Follower 666
9.4 Compensation 671
9.4.1 Theory of Compensation 671
9.4.2 Methods of Compensation 676
9.4.3 Two-Stage MOS Amplifier Compensation 681
9.4.4 Compensation of Single-Stage CMOS Op Amps 693
9.4.5 Nested Miller Compensation 696
9.5 Root-Locus Techniques 705
9.5.1 Root Locus for a Three-Pole Transfer Function 705
9.5.2 Rules for Root-Locus Construction 708
9.5.3 Root Locus for Dominant-Pole Compensation 718
9.5.4 Root Locus for Feedback-Zero Compensation 719
9.6 Slew Rate 723
9.6.1 Origin of Slew-Rate Limitations 723
9.6.2 Methods of Improving Slew Rate in Two-Stage Op Amps 725
9.6.3 Improving Slew Rate in Bipolar Op Amps 728
9.6.4 Improving Slew Rate in MOS Op Amps 729
9.6.5 Effect of Slew-Rate Limitations on Large-Signal Sinusoidal Performance 733
9.7 Effect of Feedback on a Pole-Zero Doublet 734
A.9.1 Analysis in Terms of Return-Ratio Parameters 736
A.9.2 Roots of a Quadratic Equation 737
Problems 739
References 746
Chapter 10 Nonlinear Analog Circuits 747
10.1 Introduction 747
10.2 Analog Multipliers Employing the Bipolar Transistor 747
10.2.1 The Emitter-Coupled Pair as a Simple Multiplier 748
10.2.2 The dc Analysis of the Gilbert Multiplier Cell 750
10.2.3 The Gilbert Cell as an Analog Multiplier 752
10.2.4 A Complete Analog Multiplier 755
10.2.5 The Gilbert Multiplier Cell as a Balanced Modulator and Phase Detector 756
10.3 Phase-Locked Loops 760
10.3.1 Phase-Locked Loop Concepts 760
10.3.2 The Phase-Locked Loop in the Locked Condition 762
10.3.3 Integrated-Circuit Phase-Locked Loops 771
10.4 Nonlinear Function Synthesis 775
Problems 777
References 779
Chapter 11 Noise in Integrated Circuits 781
11.1 Introduction 781
11.2 Sources of Noise 781
11.2.1 Shot Noise 781
11.2.2 Thermal Noise 785
11.2.3 Flicker Noise (1/f Noise) 786
11.2.4 Burst Noise (Popcorn Noise) 787
11.2.5 Avalanche Noise 787
11.3 Noise Models of Integrated-Circuit Components 789
11.3.1 Junction Diode 789
11.3.2 Bipolar Transistor 790
11.3.3 MOS Transistor 791
11.3.4 Resistors 798
11.3.5 Capacitors and Inductors 799
11.4 Circuit Noise Calculations 799
11.4.1 Bipolar Transistor Noise Performance 802
11.4.2 Equivalent Input Noise and the Minimum Detectable Signal 805
11.4.3 MOS Transistor Noise Performance 807
11.5 Equivalent Input Noise Generators 812
11.5.1 Bipolar Transistor Noise Generators 813
11.5.2 MOS Transistor Noise Generators 818
11.6 Effect of Feedback on Noise Performance 820
11.6.1 Effect of Ideal Feedback on Noise Performance 821
11.6.2 Effect of Practical Feedback on Noise Performance 821
11.7 Noise Performance of Other Transistor Configurations 828
11.7.1 Common-Base-Stage Noise Performance 828
11.7.2 Emitter-Follower Noise Performance 829
11.7.3 Differential-Pair Noise Performance 830
11.7.4 Super-Source-Follower Noise Performance 833
11.8 Noise in Operational Amplifiers 836
11.9 Noise Bandwidth 840
11.10 Noise Figure and Noise Temperature 845
11.10.1 Noise Figure 845
11.10.2 Noise Temperature 849
Problems 849
References 854
Chapter 12 Fully Differential Operational Amplifiers 857
12.1 Introduction 857
12.2 Properties of Fully Differential Amplifiers 857
12.3 Small-Signal Models for Balanced Differential Amplifiers 860
12.4 Common-Mode Feedback 865
12.4.1 Common-Mode Feedback at Low Frequencies 867
12.4.2 Stability and Compensation Considerations in a CMFB Loop 871
12.5 CMFB Circuits 873
12.5.1 CMFB Using Resistive Divider and Amplifier 873
12.5.2 CMFB Using Two Differential Pairs 878
12.5.3 CMFB Using Transistors in the Triode Region 880
12.5.4 Switched-Capacitor CMFB 882
12.6 Fully Differential Op Amps 885
12.6.1 A Fully Differential Two-Stage Op Amp 885
12.6.2 Fully Differential Telescopic-Cascode Op Amp 896
12.6.3 Fully Differential Folded-Cascode Op Amp 897
12.6.4 A Differential Op Amp with Two Differential Input Stages 898
12.6.5 Neutralization 899
12.7 Unbalanced Fully Differential Circuits 901
12.8 Bandwidth of the CMFB Loop 907
12.9 Analysis of a CMOS Fully Differential Folded-Cascode Op Amp 909
12.9.1 dc Biasing 911
12.9.2 Low-Frequency Analysis 914
12.9.3 Frequency and Time Responses in a Feedback Application 920
Problems 927
References 933
Index 935
CHAPTER 1
Models for Integrated-Circuit Active Devices
1.1 Introduction
The analysis and design of integrated circuits depend heavily on the utilization of suitable models for integrated-circuit components. This is true in hand analysis, where fairly simple models are generally used, and in computer analysis, where more complex models are encountered. Since any analysis is only as accurate as the model used, it is essential that the circuit designer have a thorough understanding of the origin of the models commonly utilized and the degree of approximation involved in each.
This chapter deals with the derivation of large-signal and small-signal models for integrated-circuit devices. The treatment begins with a consideration of the properties of junctions, which are basic parts of most integrated-circuit elements. Since this book is primarily concerned with circuit analysis and design, no attempt has been made to produce a comprehensive treatment of semiconductor physics. The emphasis is on summarizing the basic aspects of semiconductor-device behavior and indicating how these can be modeled by equivalent circuits.
1.2 Depletion Region of a pn Junction
The properties of reverse-biased junctions have an important influence on the characteristics of many integrated-circuit components. For example, reverse-biased junctions exist between many integrated-circuit elements and the underlying substrate, and these junctions all contribute voltage-dependent parasitic capacitances. In addition, a number of important characteristics of active devices, such as breakdown voltage and output resistance, depend directly on the properties of the depletion region of a reverse-biased junction. Finally, the basic operation of the junction field-effect transistor is controlled by the width of the depletion region of a junction. Because of its importance and application to many different problems, an analysis of the depletion region of a reverse-biased junction is considered below. The properties of forward-biased junctions are treated in Section 1.3 when bipolar-transistor operation is described.
Consider a junction under reverse bias as shown in Fig. 1.1. Assume constant doping densities of atoms/cm3 in the -type material and atoms/cm3 in the -type material. (The characteristics of junctions with nonconstant doping densities will be described later.) Due to the difference in carrier concentrations in the -type and -type regions, there exists a region at the junction where the mobile holes and electrons have been removed, leaving the fixed acceptor and donor ions. Each acceptor atom carries a negative charge and each donor atom carries a positive charge, so that the region near the junction is one of significant space charge and resulting high electric field. This is called the depletion region or space-charge region. It is assumed that the edges of the depletion region are sharply defined, as shown in Fig. 1.1, and this is a good approximation in most cases.
Figure 1.1 The abrupt junction under reverse bias . (a) Schematic. (b) Charge density. (c) Electric field. (d ) Electrostatic potential.
For zero applied bias, there exists a voltage across the junction called the built-in potential. This potential opposes the diffusion of mobile holes and electrons across the junction in equilibrium and has a value1
(1.1)where
the quantity is the intrinsic carrier concentration in a pure sample of the semiconductor and at K for silicon.
In Fig. 1.1, the built-in potential is augmented by the applied reverse bias, , and the total voltage across the junction is . If the depletion region penetrates a distance into the -type region and into the -type region, then we require
(1.2)because the total charge per unit area on either side of the junction must be equal in magnitude but opposite in sign.
Poisson's equation in one dimension requires that
(1.3)where is the charge density, is the electron charge ( coulomb), and is the permittivity of the silicon ( farad/cm). The permittivity is often expressed as
(1.4)where is the dielectric constant of silicon and is the permittivity of free space ( F/cm). Integration of (1.3) gives
(1.5)where is a constant. However, the electric field is given by
(1.6)Since there is zero electric field outside the depletion region, a boundary condition is
and use of this condition in (1.6) gives
(1.7)Thus the dipole of charge existing at the junction gives rise to an electric field that varies linearly with distance.
Integration of (1.7) gives
(1.8)If the zero for potential is arbitrarily taken to be the potential of the neutral -type region, then a second boundary condition is
and use of this in (1.8) gives
(1.9)At , we define , and then (1.9) gives
(1.10)If the potential difference from to is , then it follows that
(1.11)and thus the total voltage across the junction is
(1.12)Substitution of (1.2) in (1.12) gives
(1.13)From (1.13), the penetration of the depletion layer into the -type region is
(1.14)Similarly,
(1.15)Equations 1.14 and 1.15 show that the depletion regions extend into the -type and -type regions in inverse relation to the impurity concentrations and in proportion to . If either or is much larger than the other, the depletion region exists almost entirely in the lightly doped region.
EXAMPLE
An abrupt junction in silicon has doping densities atoms/cm3 and atoms/cm3. Calculate the junction built-in potential, the depletion-layer depths, and the maximum field with 10 V reverse bias.
From (1.1),
From (1.14), the depletion-layer depth in the -type region is
The depletion-layer depth in the more heavily doped -type region is
Finally, from (1.7), the maximum field that occurs for is
Note the large magnitude of this electric field.
1.2.1 Depletion-Region Capacitance
Since there is a voltage-dependent charge associated with the depletion region, we can calculate a small-signal capacitance as follows:
(1.16)Now
(1.17)where is the cross-sectional area of the junction. Differentiation of (1.14) gives
(1.18)Use of (1.17) and (1.18) in (1.16) gives
(1.19)The above equation was derived for the case of reverse bias applied to the diode. However, it is valid for positive bias voltages as long as the forward current flow is small. Thus, if represents the bias on the junction (positive for forward bias, negative for reverse bias), then (1.19) can be written as
(1.20) (1.21)where is the value of for .
Figure 1.2 Charge density versus distance in a graded junction.
Figure 1.3 Behavior of junction depletion-layer capacitance as a function of bias voltage .
Equations 1.20 and 1.21 were derived using the assumption of constant doping in the -type and n-type regions. However, many practical diffused junctions more closely approach a graded doping profile, as shown in Fig. 1.2. In this case, a similar calculation yields
(1.22)Note that both (1.21) and (1.22) predict values of approaching infinity as approaches . However, the current flow in the diode is then appreciable and the equations are no longer valid. A more exact analysis[2, 3] of the behavior of as a function of gives the result shown in Fig. 1.3. For forward-bias voltages up to about , the values of predicted by (1.21) are very close to the more accurate value. As an approximation, some computer programs approximate for by a linear extrapolation of (1.21) or (1.22).
EXAMPLE
If the zero-bias capacitance of a diffused junction is 3 pF and V, calculate the capacitance with 10 V reverse bias. Assume the doping profile can be approximated by an abrupt junction.
From (1.21),
1.2.2 Junction Breakdown
From Fig. 1.1c, it can be seen that the maximum electric field in the depletion region occurs at the junction; and for an abrupt junction, (1.7) yields a value
(1.23)Substitution of (1.14) in (1.23) gives
(1.24)where has been neglected. Equation 1.24 shows that the maximum field increases as the...
