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Timing Characterization of a Semiconductor Random-Access Memory

The timing characteristics define the templates of the times of all signals. When designing a computer, the engineer must respect these while ensuring that those of the bus and the master of exchanges, i.e. a microprocessor or a controller, are also respected. Three standardization offices or professional associations have standardized the times specific to memory. These are the International Electrotechnical Commission (IEC), the Institute of Electrical and Electronics Engineers (IEEE) and the Joint Electron Device Engineering Council (JEDEC) (Solid State Technology Association)). Only the most widely used, i.e. the last two, are presented. Let us first give the decoding keys of a timing diagram describing the operation of a memory.

1.1. Signal naming convention

For this work, the signal naming convention is as follows. The name of a signal generally begins with a capital letter. The names of the signals follow standards such as IEEE 662-1992 (IEEE 1992) and JEDEC no. 100B.01 (JEDEC 2002) and JESD 21-C (JEDEC 2003), as summarized in Table 1.1.

To indicate an active-low state of a signal, the signal name is prefixed, for example, with a "#" as in this work, a "-" (i.e. minus sign), a "/" or a "Not_". The absence of a prefix indicates that the signal is active-high. Let us take an example with the reset signal, which is most often active-low: it is therefore named #Reset. If the activity occurs on an edge, the name will be prefixed by "F_" or "#F_" for, respectively, a positive or negative active edge.

Table 1.1. Standardized signal names

Designation JEDEC IEEE Address A - Shift clock C - Column address CA - Column address strobe CAS CE Data input D - Data input/output DQ - Chip enable E - Erasure ER - Output enable G - Program PR P Data output Q - Read R - Row address RA - Row address strobe RAS RE Refresh RF or F - Read/write RW - Chip select S - Write (write enable) W -

1.2. Timing diagram

A timing diagram makes it possible to graphically represent the evolution of a logic signal over time. To make reading easier, the time axis (abscissa) is implicit. We already presented this during the study of combinational and sequential logic in section 3.2.3 of Darche (2002). In a timing diagram, the ordinate represents the binary logic states low (L) and high (H), as shown in Figure 1.1. Let us recall that in positive logic (see section 2.2.1 of Darche (2004)), the H and L levels represent, respectively, a logic state of 1 and 0. When it concerns an input signal, it is a requirement. When it is an output signal, it describes the operation of the logic system. The signal name is indicated to its left. When the signal is in high impedance, it is represented symbolically between the two valid logic states. The state not being defined, it is called "floating". It is then considered that there exists a third state noted Z (high impedance state or Z-state). It has no physical reality. It only indicates that an output stage of a logic operator is disconnected. But usage makes people talk about three-state or tristateT logic. This Z-state is represented in a timing diagram in the center, between states 1 and 0. The subject was developed in section 2.2.1 of Darche (2004). When the signal is at a logic state 0 or 1, the signal is in low impedance. IEEE 662-1992 adds a voltage level S, higher than the high logic level, generally used for programming reprogrammable read-only memories (see Volume 6).

Figure 1.1. The decoding keys of a timing diagram: the four permanent states

A "don't care" state is indicated by hatching or shading (see Figure 1.2). For an input, this means that a change of its state is allowed. For an output, its state does not matter (state X or don't care state) or it is not defined (undefined). It varies and is not known.

Figure 1.2. The don't care state X

IEEE 662-1992 specifies a valid state (V). Figure 1.3 shows a state that must be valid for an input or that will be valid in the case of an output. This form is generally used to describe the behavior of a group of signals, for example, those of a bus. The crossing point marks a valid value change.

Figure 1.3. The decoding keys of a timing diagram: the valid state V of a permanent signal with indication of a change point

The different standardized states of a timing diagram are summarized in Table 1.2.

Table 1.2. The different standardized states or levels of a timing diagram in the IEEE 662-1992 and JEDEC standards

Letter Label State H High logic level High L Low logic level Low S Super high level (IEEE) Voltage higher than the positive supply voltage (VCC or VDD), IEEE only V Valid steady-state level (JEDEC) Constant valid X Invalid (IEEE)
Unknown, changing, or don't care level JEDEC Undefined or don't care Z OFF (IEEE)
High impedance state of three-state output (JEDEC) High impedance

A state change is marked by a slash indicating the physical variation of the amplitude of the electrical signal (see Figure 1.4). For a perfect signal, the slash would be vertical but that cannot be physical reality, since a physical quantity only varies continuously. If this change must take place within a time interval, then the lower and upper bounds are indicated (time markers 1-2 and 3-4 in the figure). Hatching then fills the area. Shading has a stronger meaning because the state of the signal is indeterminate (state X). This means it can vary from one state to the other several times. Figure 1.4 shows the two possible transitions, from low state to high state for the upper part of the figure, and from high state to low state for the lower part. Returning to the initial state is not allowed.

Figure 1.4. The decoding keys of a timing diagram: the state change of a signal

Figure 1.5. The decoding keys of a timing diagram: the state change of a signal

Figure 1.5 shows variants. Let us take the case of Figure 1.5(a). Between markers 1 and 2 or between markers 3 and 4, the signal has a stable state. Before, it is in a valid state. However, it must imperatively be at the required logic state before marker 1 or 3. After marker 2 or marker 4, the state becomes indeterminate. In the other case, before marker 1 or 3, the signal is in a stable state. For the upper version, if it is at high state, it will or must go to low state before time marker 1. For the lower version, if it is at low state, it will or must go to high state before time marker 3. A time tolerance or an uncertainty (if not quantified) is thus introduced.

Figure 1.6 shows the transition of an output from a low impedance state (i.e. 1 or 0) to a high impedance state noted Z. An output of a logic operator or an electrical line is said to be in high impedance when no electrical source powers it. For a totem-pole-type output (see sections 2.2.1 and 2.3.2 of Darche (2004)), this means that the two output transistors are blocked. There are thus four cases, which are the transition from state 0 to state Z, the reverse, from 1 to Z, and vice versa.

Figure 1.6. The decoding keys of a timing diagram: the transition of a signal from a low impedance state to a Z state and vice versa

Figure 1.7 is a generalization of the previous cases. This timing diagram generally applies to a group of signals, for example, those of a bus. Each of them can take any value until the bus goes into high impedance, and therefore all the signals.

Figure 1.7. The decoding keys of a timing diagram: the transition from a Z...