Yield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford

Preface. Programme committee. List of contributors. Prologue. Yield loss mechanisms and defect tolerance. Alternative perspectives (4 papers). Catastrophic Yield Loss Models (4 papers). Parametric yield loss (3 papers). Defect-tolerant architectures (4 papers). Yield prediction with defect tolerance (4 papers). Testing (3 papers). Index.