Advanced Ultra Low-Power Semiconductor Devices
Description
Written and edited by a team of experts in the field, this important new volume broadly covers the design and applications of metal oxide semiconductor field effect transistors.
This outstanding new volume offers a comprehensive overview of cutting-edge semiconductor components tailored for ultra-low power applications. These components, pivotal to the foundation of electronic devices, play a central role in shaping the landscape of electronics. With a focus on emerging low-power electronic devices and their application across domains like wireless communication, biosensing, and circuits, this book presents an invaluable resource for understanding this dynamic field.
Bringing together experts and researchers from various facets of the VLSI domain, the book addresses the challenges posed by advanced low-power devices. This collaborative effort aims to propel engineering innovations and refine the practical implementation of these technologies. Specific chapters delve into intricate topics such as Tunnel FET, negative capacitance FET device circuits, and advanced FETs tailored for diverse circuit applications.
Beyond device-centric discussions, the book delves into the design intricacies of low-power memory systems, the fascinating realm of neuromorphic computing, and the pivotal issue of thermal reliability. Authors provide a robust foundation in device physics and circuitry while also exploring novel materials and architectures like transistors built on pioneering channel/dielectric materials. This exploration is driven by the need to achieve both minimal power consumption and ultra-fast switching speeds, meeting the relentless demands of the semiconductor industry. The book's scope encompasses concepts like MOSFET, FinFET, GAA MOSFET, the 5-nm and 7-nm technology nodes, NCFET, ferroelectric materials, subthreshold swing, high-k materials, as well as advanced and emerging materials pivotal for the semiconductor industry's future.
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Persons
Shubham Tayal, PhD, is an assistant professor in the Department of Electronics and Communication Engineering at SR University, Warangal, India. He has more than six years of academic and research experience and has published more than 30 research papers in various scholarly journals and conferences. He is on the editorial and reviewer panel of many journals and conferences, as well. He is the editor or coeditor of seven books and was a recipient of the Green ThinkerZ International Distinguished Young Researcher Award in 2020.
Abhishek Kumar Upadhyay, PhD, is a research and development engineer at X-FAB GmbH Dresden, Germany. After obtaining his PhD in electrical engineering from the Indian Institute of Technology in 2019, he worked for one year as a postdoctoral fellow in the Model Group, Material to System Integration Laboratory, University of Bordeaux, France, and has worked in the industry since. He has authored several research articles.
Shiromani Balmukund Rahi, PhD, is a faculty member at the Mahamaya College of Agriculture Engineering and Technology, Akabarpur, Uttar Pradesh, India and an associated senior research scholar of Department of Electrical Engineering(Semiconductor Device, modeling division), Indian Institute of Technology Kanpur. He has more than six years of academic and research experience and has published 25 journal articles, two proceedings, and 18 book chapters, and he has edited seven books for international publications.
Young Suh Song is an assistant professor in the Department of Computer Science at the Korea Military Academy. He has authored or co-authored over 40 research papers in journals and conferences, and he has served as a technical committee member and guest speaker at various universities and conferences.
Content
Preface xi
1 Subthreshold Transistors: Concept and Technology 1
Ball Mukund Mani Tripathi
1.1 Introduction 2
1.2 Major Sources of Leakage and Possible Methods of Prevention 2
1.3 Possibilities and Challenges 12
1.4 Conclusions 21
2 Introduction to Conventional MOSFET and Advanced Transistor TFET 29
M. Saravanan, K. Ramkumar, Eswaran Parthasarathy, J. Ajayan and S. Sreejith
2.1 Introduction 30
2.2 Device Structure 30
2.3 TFET Principle of Operation 31
2.4 Material Characterization 33
2.5 Characteristics of TFET 35
2.6 Comparison of OFF-State Characteristics 37
2.7 Phonon Scattering's Impact 39
2.8 ON-State Performance Comparison 40
2.9 Performance Analysis Based on Intrinsic Delay 40
2.10 Bandgap's Effect on Device Performance 41
2.11 MOSFET and TFET Scaling Behaviour 43
2.12 Surface Potential of an N-TFET and N-MOSFET 45
2.13 Professional Advantages of TFET over MOSFET 46
2.14 Conclusion 46
3 Operation Principle and Fabrication of TFET 51
Mekonnen Getnet Yirak and Rishu Chaujar
3.1 Introduction 52
3.2 Planar MOSFET's Limitations 54
3.3 Demand for Low Power Operation 55
3.4 TFET: Operation Principle of TFET 56
3.5 TFET: Recent Design Issues in TFET 63
3.6 TFET: Modeling and Application 65
3.7 TFET: Fabrication Perspective 68
3.8 TFET: Applications and Future of Low-Power Electronics 70
3.9 Expected Challenges in Replacing MOSFET with TFET 70
3.10 Conclusion 71
4 Mathematical Modeling of TFET and Its Future Applications: Ultra Low-Power SRAM Circuit and III-IV TFET 77
Nayana G H and P. Vimala
4.1 Introduction 78
4.2 Modeling Approaches 78
4.3 Structure 81
4.4 Applications of Tunnel Field-Effect Transistor 83
4.5 Road Ahead for Tunnel Field Effect Transistors 87
5 Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency Performance of F-TFET 91
Prabhat Singh and Dharmendra Singh Yadav
5.1 Introduction 92
5.2 Simulated Device Structure and Parameters 93
5.3 DC Characteristics 93
5.4 Analysis of Analog/RF FOMs 98
5.5 Conclusion 101
6 Comparative Study of Gate Engineered TFETs and Optimization of Ferroelectric Heterogate TFET Structure 105
Susmitha Kothapalli, Zohmingliana and Brinda Bhowmick
6.1 Introduction 106
6.2 Study of Different TFET Structures 106
6.3 Proposed Structure 109
6.4 Results and Discussion 110
6.5 Conclusion 127
6.6 Future Scope 128
7 State of the Art Tunnel FETs for Low Power Memory Applications 131
Arun A. V., Sreelekshmi P. S. and Jobymol Jacob
7.1 Static Random Access Memory 131
7.2 Performance Parameters of SRAM Cell 134
7.3 TFET-Based SRAM Cell Design 135
7.4 Conclusion 159
8 Epitaxial Layer-Based Si/SiGe Hetero-Junction Line Tunnel FETs: A Physical Insight 165
Abhishek Acharya, Sourabh Panwar, Shobhit Srivastava and Shashidhara M.
8.1 Fundamental Limitation of CMOS: Tunnel FETs 165
8.2 Working Principle of Tunnel FET 168
8.3 Point and Line TFETs: Tunneling Direction 169
8.4 Perspective of Line TFETs 170
8.5 Analytical Models of Line TFETs 176
8.6 Line TFETs for Analog & Digital Circuits Design 178
8.7 Other Steep Slope Devices 179
8.8 Conclusion 181
9 Investigation of Thermal Performance on Conventional and Junctionless Nanosheet Field Effect Transistors 187
Sresta Valasa, Shubham Tayal and Laxman Raju Thoutam
9.1 Introduction 188
9.2 Device Simulation Details 190
9.3 Results and Discussion 192
9.4 Conclusion 201
10 Introduction to Newly Adopted NCFET and Ferroelectrics for Low-Power Application 207
Shelja Kaushal
10.1 Introduction 208
10.2 NCFET and Its Design Constraints 209
10.3 NCFET for Low-Power Applications 216
10.4 Summary 226
11 Application of Ferroelectrics: Monolithic-3D Inference Engine with IGZO Based Ferroelectric Thin Film Transistor Synapses 235
Sourav De, Maximilian Lederer, Yannick Raffel, David Lehninger, Sunanda Thunder, Michael P.M. Jank, Tarek Ali and Thomas Kämpfe
11.1 Introduction 236
11.2 Ferroelectricity in Hafnium Oxide 241x Contents
11.3 IGZO Based Ferroelectric Thin Film Transistor 245
11.4 Applications in Neural Networks 249
11.5 Conclusion 250
12 Radiation Effects and Their Impact on SRAM Design: A Comprehensive Survey with Contemporary Challenges 261
Y. Alekhya, Umakanta Nanda and Chandan Kumar Pandey
12.1 Introduction 261
12.2 Literature Survey 263
12.3 Impact of Radiation Effects on Sram Cells 266
12.4 Results and Discussion 267
12.5 Conclusion 274
13 Final Summary and Future of Advanced Ultra Low Power Metal Oxide Semiconductor Field Effect Transistors 279
Young Suh Song, Shiromani Balmukund Rahi, Shahnaz Kossar, Abhishek Kumar Upadhyay, Shubham Tayal, Chandan Kumar Pandey and Biswajit Jena
13.1 Introduction 280
13.2 Challenges in Future Ultra-Low Power Semiconductors 282
13.3 Conclusion 286
References 288
Index 293
1
Subthreshold Transistors: Concept and Technology
Ball Mukund Mani Tripathi
Electronics and Communication Engineering, Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, Andhra Pradesh, India
Abstract
The continuous downscaling of Si MOS transistors facilitated technology to follow Moor's Law which states that transistor density doubles every 18 months. However, the fundamental material limitation of Si, popularly known as Boltzmann's tyranny, sets a limit on the subthreshold swing up to 60mV/ decade, which means the minimum voltage required for a decade of change in the current is 60 mV. In addition, the various short channel effects, including VT roll-off, increasing IOFF, DIBL, and GIDL, also increase with downscaling. These two effects decrease the ION/IOFF ratio and increase the power dissipation in the transistor, which is very significant, particularly in sub-nanometre technology. So, it is pertinent to think about applications where subthreshold current can be utilized, particularly in ultra-low power and very low-power applications. In the past few years, subthreshold region operation has gained attention and encouraging results have been reported. The presented chapter deals with the scope, challenges, and possible solutions for subthreshold transistors. It also presents developments in the recent past, new devices, structures, and materials with better subthreshold performance, such as high-k transistors, transistors on SOI, thin film transistors, multi-gate transistors, FinFETs, gate-all-around transistors, nanowire, Nano sheet, and TFETs. Recently, NCFET also reported it promises to improve subthreshold performance without changing the conventional structure of the transistor, which is encouraging.
Keywords: Subthreshold transistor, tunnel FET, NC FET, scaling
1.1 Introduction
The market for power-efficient systems, such as personal digital assistants, cellular phones, and other communication devices, has grown significantly due to the fast growth of battery-operated portable applications. To meet the demand, the size of the transistor and supply voltages are scaled down. But, as the size of the transistor is getting smaller at every technology node to increase functionality and high performance, various leakages, such as sub-threshold leakage current increase, gate leakage, and band-to-band tunneling (BTBT) currents through source/drain-substrate junctions are also increasing. These leakages deteriorate device performance and inhibit further downscaling. To overcome these issues, exhaustive research has been carried out in the past that is still going on, such as a reduction in switching frequency and the development of new architectures for pipelining, connections, and logic optimization. Unfortunately, this is not sufficient for future demands for ultra-low power applications below Giga Hertz frequency applications, e.g., instruments used in medical and portable applications. Therefore, various design techniques have been proposed for power-efficient applications and subthreshold transistors are one of them. The subthreshold transistors, as the name suggests, are operated below the threshold voltage or in the subthreshold region [1-4]. The subthreshold current, which is known as the leakage current in conventional terms, can be used for ultra-low power applications. In the subthreshold region, transistors have ideal voltage transfer characteristics, high trans-conductance, and lower gate input capacitance compared to the inversion region and are therefore better for logic circuits. It provides power efficiency at the cost of performance and can be a future choice for ultra-low-power digital and memory applications [5-7]. This chapter is organized as follows. In Section 1.2, the major sources of subthreshold leakage and their possible methods of prevention are analyzed. Various challenging issues confronting the current and future robust subthreshold circuit design are discussed and the scope of subthreshold technology is also presented in Section 1.3. Finally, conclusions are drawn in Section 1.4.
1.2 Major Sources of Leakage and Possible Methods of Prevention
1.2.1 Leakage Mechanisms in MOS Transistors
In Figure 1.1 the various sources of leakage are shown: reverse-bias PN junction leakage (I1); subthreshold leakage (I2); oxide tunneling current (I3); gate current due to hot-carrier injection (I4); GIDL (I5); and channel punch through current (I6). The leakage current components in 2, 5, and 6 are offstate leakage mechanisms, 1 and 3 occur in both ON and OFF states, and 4 occurs in the OFF state.
Figure 1.1 Major components of leakage [8].
1.2.1.1 Current I1
This current is due to leakage through reverse-biased drain/source PN junctions and electron-hole pair generation in the depletion region. Additionally, leakage also occurs through overlapping gates to the drainwell PN junctions or carrier generation in drain-to-well depletion regions. Shallow junctions with high doping are used to overcome this leakage, but it also enhances band-to-band tunneling (BTBT) leakage [9].
1.2.1.1.1 Band-to-Band Tunnelling (BTBT) Current
The electric field increases up to 106 V/cm due to heavily doped shallow junctions, which facilitate quantum mechanical band-to-band tunneling (BTBT) across the reverse-biased PN junction and, therefore, tunneling leakage increases. Considering the step junction, the mathematical expression for tunneling current density is as follows [9]:
where q, h, m*, EG, VRB, E, NA, ND, and Vbi are electronic charge, Planck's constant, effective mass of electron, energy-band gap, applied reverse bias, electric field at the junction doping on the p side, doping on the n side, permittivity of silicon, and built-in voltage across the junction, respectively. In state-of-the-art technology, smaller node devices are used where abrupt and high doping concentration profiles are used and therefore, BTBT leakage through the drain-well junction is high.
1.2.1.2 Current I2
Above the threshold, voltage channel is said to be fully inverted and its concentration is compared to the bulk concentration, while below the threshold voltage, the channel is not fully inverted, but the channel has some charge and it is weakly inverted. Therefore, the leakage current varies exponentially with gate voltage flows in the device. This current is primarily diffusion current because most of the voltage drop occurs across the drain substrate PN junction, which is inherently reverse-biased. So, the vertical and horizontal fields in the channel do not vary significantly and the drift current is less compared to the diffusion current, unlike in the strong inversion region where the drift current dominates over the diffusion current. The mathematical expression of the subthreshold leakage current is as follows [10]:
where VTH, VT, COX, µ0, ?, TD, CD, and TOX are the threshold voltage, thermal voltage, gate oxide capacitance, zero bias mobility, body effect coefficient, maximum depletion layer width, depletion layer capacitance, and the thickness of the gate oxide. Another important parameter in the sub-threshold region is the subthreshold slope, which indicates the speed of turning off the transistor below the threshold voltage and is given by [10].
The lower the value of SS, the better the device is. At 300 K, its minimum value is 60mV/decade. As suggested by the expression, the lower value can be obtained by reducing temperature T, higher Cox or a thinner oxide layer, and lower Cdm or a thicker depletion layer or lower substrate doping.
1.2.1.2.1 DIBL (Drain-Induced Barrier Lowering)
Ideally, the drain voltage should have a minimum effect on the source-channel barrier or the threshold voltage of the MOSFETs.
In real devices, particularly the short-channel ones, drain voltage affects the channel conduction and the barrier between the source and channel at high drain voltage. This is known as the drain induced barrier-lowering phenomenon and thus, the drain voltage directly affects the threshold voltage along with the gate voltage. The shorter the device, the greater the impact of DIBL. Therefore, this increases the subthreshold leakage and lowers the subthreshold slope significantly as we go to smaller nodes [11]. To reduce DIBL, shallow junctions at the source and drain and higher channel doping are used [11-13].
1.2.1.2.2 Effect of Body Bias
As the expression of threshold voltage indicates, it increases with increasing reverse body bias and therefore, the off current decreases.
where VTH, VFB, NA, ?, VBS, and, ? are threshold voltage, flat-band voltage, doping density in the substrate, difference between the Fermi potential and the intrinsic potential in the substrate, and substrate sensitivity. The expression of subthreshold leakage including weak inversion, DIBL, and body effect is as follows [14]:
VTH0 is the zero bias threshold voltage and VT is the thermal voltage. The effect of body bias for small voltage is linear and aVSa is the linearized body effect coefficient. ? is the DIBL coefficient, COX is the gate oxide capacitance, µ0 is the zero-bias mobility, and m is the subthreshold swing coefficient of the transistor. ?VTH is a term introduced to account for transistor-to-transistor leakage variations.
1.2.1.2.3 Effect of Width Narrowing
The effect of the...
