Practical Microcontroller Engineering with ARM- Technology
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Content
Preface xxix
Acknowledgments xxxi
Trademarks and Copyrights xxxiii
Copyright Permissions xxxv
About the Companion Website xxxix
Chapter 1 Introduction to Microcontrollers and This Book 1
1.1 Microcontroller Configuration and Structure 2
1.2 The ARM® Cortex®M4 Microcontroller System 3
1.3 The TM4C123GH6PM Microcontroller Development Tools and Kits 4
1.4 Outstanding Features About This Book 5
1.5 Who This Book Is For 5
1.6 What This Book Covers 6
1.7 How This Book Is Organized and How to Use This Book 8
1.8 How to Use the Source Code and Sample Projects 9
1.9 Instructors and Customers Supports 11
Chapter 2 ARM® Microcontroller Architectures 13
2.1 Overview and Introduction 13
2.2 Introduction to ARM® Cortex®-M4 MCU 15
2.2.1 The Architecture of ARM® Cortex®-M4 MCU 17
2.3 The Memory Architecture 27
2.3.1 The Memory Map 28
2.3.2 The Stack Memory 29
2.3.3 The Program Models and States 32
2.3.4 The Memory Protection Unit (MPU) 33
2.4 The Nested Vectored Interrupt Controller (NVIC) Architecture 34
2.4.1 The Nested Vectored Interrupt Controller (NVIC) Features 35
2.4.2 Exception and Interrupt Sources 35
2.4.3 Exception Priority Levels and Mask Registers 35
2.4.4 Respond and Process Exceptions and Interrupts 36
2.4.5 Exception and Interrupt Vector Table 37
2.5 The Debug Architecture 37
2.6 Introduction to TivaTM C Series ARM® Cortex®-M4 MCU-TM4C123GH6PM 38
2.6.1 TM4C123GH6PM Microcontroller Overview 39
2.6.2 TM4C123GH6PM Microcontroller On-Chip Memory Map 40
2.6.3 TM4C123GH6PM Microcontroller General-Purpose Input-Output (GPIO) Module 44
2.6.4 TM4C123GH6PM Microcontroller System Controls 57
2.7 Introduction to TivaTM C Series LaunchPadTM TM4C123GXL Evaluation Board 72
2.8 Introduction to EduBASE ARM® Trainer 77
2.9 Chapter Summary 77
Homework 79
Chapter 3 ARM® Microcontroller Development Kits 83
3.1 Overview and Introduction 83
3.2 The Entire TivaTM TM4C123G-based Development System 84
3.3 Download and Install Development Suite and Specified Firmware 86
3.4 Introduction to the Integrated Development Environment-Keil® MDK µVersion5 87
3.4.1 The Keil® MDK-ARM® for the MDK-Cortex-M Family 88
3.4.2 General Development Flow with MDK-ARM® 89
3.4.3 Warming Up Keil® MDK Cortex-M Kit with Example Projects 91
3.4.4 The Functions of the Keil® MDK-ARM® µVersion®5 GUI 95
3.5 Embedded Software Development Procedure 127
3.6 The Keil® ARM® -MDK µVision5 Debugger and Debug Process 128
3.6.1 The ARM® µVision5 Debug Architecture 129
3.6.2 The ARM® Debug Adaptor and Debug Adaptor Driver 130
3.6.3 TivaTMCSeries LaunchPadTM Debug Adaptor and Debug Adaptor Driver 132
3.6.4 The ARM® µVersion5 Debug Process 133
3.6.5 The ARM® Trace Feature 134
3.6.6 The ARM® Instruction Set Simulator 136
3.6.7 The ARM® Programs Running from SRAM 137
3.6.8 ARM® Optimizations 139
3.7 The TivaWareTM for C Series Software Suite 140
3.7.1 The TivaWareTM C Series Software Package 142
3.7.2 TivaWareTM C Series for TM4C123G LaunchPadTM Evaluation Kit 145
3.8 The TivaWareTM for C Series Utilities and Other Supports 147
3.8.1 Additional Utilities Provided by TivaWareTM for C Series 148
3.9 Program Examples 151
3.10 Chapter Summary 152
Homework 152
Chapter 4 ARM® Microcontroller Software and Instruction Set 155
4.1 Overview and Introduction 155
4.2 Introduction to ARM® Cortex® -M4 Software Development Structure 156
4.3 Introduction to ARM® Cortex® -M4 Assembly Instruction Set 157
4.3.1 The ARM®Cortex®-M4 Assembly Language Syntax 158
4.3.2 The ARM® Cortex®-M4 Pseudo Instructions 160
4.3.3 The ARM® Cortex®-M4 Addressing Modes 161
4.3.4 The ARM® Cortex®-M4 Instruction Set Categories 172
4.4 ARM® Cortex®-M4 Software Development Procedures 196
4.5 Using C Language to Develop ARM® Cortex®-M4 Microcontroller Applications 197
4.5.1 The Standard Data Types Used in Intrinsic Functions 198
4.5.2 The CMSIS-Core-Specific Intrinsic Functions 200
4.5.3 The Keil® ARM® Compiler-Specific Intrinsic Functions 202
4.5.4 Inline Assembler 204
4.5.5 Idiom Recognition 205
4.5.6 C Programming Development Guideline and Procedure 206
4.5.7 The TivaWareTM Peripheral Driver Library 213
4.6 Chapter Summary 243
Homework 244
Chapter 5 ARM® Microcontroller Interrupts and Exceptions 261
5.1 Overview and Introduction 261
5.2 Exceptions and Interrupts in the ARM® Cortex®-M4 MCU System 263
5.2.1 Exception and Interrupt Types 265
5.2.2 Exceptions and Interrupts Management 265
5.2.3 Exception and Interrupt Processing 268
5.3 Exceptions and Interrupts in the TM4C123GH6PM Microcontroller System 273
5.3.1 Local Interrupt Configurations and Controls for GPIO Pins 273
5.3.2 Local Interrupt Configurations and Controls for GPIO Ports 276
5.3.3 Global Interrupt Configurations and Controls 281
5.3.4 The Vector Table and Vectors Used in the TM4C123GH6PM MCU 282
5.3.5 The GPIO Interrupt Handling and Processing Procedure 284
5.4 Developing GPIO Port Interrupt Projects to Handle GPIO Interrupts 285
5.4.1 Two Software Packages Used in the TM4C123GH6PM MCU System 286
5.4.2 Using DRA Programming Model to Handle GPIO Interrupts 290
5.4.3 Using CMSIS Core Macros for NVIC Registers to Handle GPIO Interrupts 294
5.4.4 Using TivaWareTM Peripheral Driver Library API Functions to Handle GPIO Interrupts 306
5.4.5 Using CMSIS Core Access Functions to Handle GPIO Interrupts 313
5.5 Comparison Among Four Interrupt Programming Methods 317
5.6 Chapter Summary 318
Homework 319
Chapter 6 ARM® Microcontroller Memory System 333
6.1 Overview and Introduction 333
6.2 Memory Architecture in the TM4C123GH6PM MCU System 334
6.2.1 Static Random Access Memory (SRAM) 336
6.2.2 Flash Memory 336
6.2.3 Flash Memory Protection Control 349
6.2.4 Internal Read-Only Memory (ROM) 351
6.2.5 Electrical Erased Programmable Read-Only Memory (EEPROM) 354
6.3 Memory Map in TM4C123GH6PM MCU System 361
6.4 Bit-Band Operations 362
6.4.1 The Mapping Relationship Between the Bit-Band Region and the Bit-Band Alias Region 365
6.4.2 The Advantages of Using the Bit-Band Operations 365
6.4.3 An Illustration Example of Using Bit-Band Alias Addresses 367
6.4.4 Bit-Band Operations for Different Data Sizes 369
6.4.5 Bit-Band Operations Built in C Programs 369
6.5 Memory Requirements and Memory Properties 370
6.5.1 Memory Requirements 371
6.5.2 Memory Access Attributes 372
6.5.3 Memory Endianness 373
6.6 Memory System Programming Methods 375
6.6.1 The API Functions Used for Flash Memory Programming 376
6.6.2 The API Functions Used for EEPROM Programming 378
6.7 Memory System Programming Projects 380
6.7.1 Flash Memory Programming 380
6.7.2 EEPROM Programming 401
6.7.3 Three Kinds of System Header Files in the TM4C123GH6PM MCU System 405
6.7.4 Build Example EEPROM Programming Projects 408
6.8 Chapter Summary 420
Homework 421
Chapter 7 ARM® Cortex®-M4 Parallel I/O Ports Programming 433
7.1 Overview and Introduction 433
7.2 GPIO Module Architecture and GPIO Port Configuration 434
7.3 GPIO Port Control Registers 437
7.3.1 GPIO Port Initialization and Configuration 438
7.4 On-Board Keypad Interface Programming Project 440
7.4.1 The Keypad Interfacing Programming Structure 441
7.4.2 Create the Keypad Interfacing Programming Project (Polling-Driven) 442
7.4.3 Set Up the Environment to Build and Run the Project 446
7.5 Analog-to-Digital Converter Programming Project 446
7.5.1 ADC Modules in the TM4C123GH6PM MCU System 446
7.5.2 ADC Module Architecture and Functional Block Diagram 447
7.5.3 ADC Module Components and Signal Descriptions 448
7.5.4 Analog-to-Digital Converter 470
7.5.5 Initialization and Configuration 473
7.5.6 Build the Analog-to-Digital Converter Programming Project 475
7.5.7 ADC Module API Functions Provided in the TivaWareTM Peripheral Driver Library 480
7.6 PWM-Controlled DC and Step Motors Programming Project 486
7.6.1 The PWM Principle and Implementations 487
7.6.2 PWM Modules in the TM4C123GH6PM MCU System 487
7.6.3 PWM Generator Functional Block Diagram 490
7.6.4 PWM Module Architecture and Functional Block Diagram 502
7.6.5 PWM Module Components and Signal Descriptions 509
7.6.6 PWM Module Initialization and Configuration 513
7.6.7 PWM Module Architecture in the EduBASE ARM® Trainer 515
7.6.8 Build an Example PWM Programming Project 516
7.7 The PWM API Functions in the TivaWareTM Peripheral Driver Library 521
7.7.1 PWM Modules and Generators Configuration and Set Up Control Functions 521
7.7.2 PWM Output Control Functions 523
7.7.3 PWM Interrupt and Fault Control Functions 523
7.8 Chapter Summary 525
Homework 527
Chapter 8 ARM® Cortex®-M4 Serial I/O Ports Programming 547
8.1 Overview and Introduction 547
8.2 GPIO Module Architecture and GPIO Port Configuration 548
8.3 Synchronous Serial Interface (SSI) 551
8.3.1 Asynchronous and Synchronous Communication Protocols and Data Framing 552
8.3.2 Synchronous Serial Interface Architecture and Functional Block Diagram 555
8.3.3 The Synchronous Data Transmission Format and Frame 556
8.3.4 SSI Module Components and Signal Descriptions 560
8.3.5 Build the On-Board LCD Interface Programming Project 572
8.3.6 Build On-Board 7-Segment LED Interface Programming Project 589
8.3.7 Build Digital-to-Analog Converter Programming Project 595
8.3.8 SSI API Functions Provided by TivaWareTM Peripheral Driver Library 604
8.4 Inter-Integrated Circuit (I2C) Interface 611
8.4.1 I2C Module Bus Configuration and Operational Status 612
8.4.2 I2C Module Architecture and Functional Block Diagram 613
8.4.3 I2C Module Data Transfer Format and Frame 614
8.4.4 I2C Module Operational Sequence 614
8.4.5 I2C Module Major Operational Components and Control Signals 618
8.4.6 I2C Module Running Speeds (Clock Rates) and Interrupts 620
8.4.7 I2C Interface Control Signals and GPIO I2C Control Registers 622
8.4.8 I2C Module Control Registers and Their Functions 623
8.4.9 I2C Module Initializations and Configurations 630
8.4.10 Build an Example I2C Module Project 631
8.4.10.1 The BQ32000 Real Time Clock (RTC) 631
8.4.10.2 The Interface Between the BQ32000 and EduBASE ARM® Trainer 633
8.4.10.3 Create a DRA Model I2C Project DRAI2C 634
8.4.10.4 Create the Source File DRAI2C 634
8.4.10.5 Set Up the Environment to Build and Run the Project 638
8.4.11 I2C API Functions Provided by TivaWareTM Peripheral Driver Library 639
8.4.11.1 Master Operations 639
8.4.11.2 I2C Module Status and Initialization API Functions 640
8.4.11.3 I2C Module Sending and Receiving Data API Functions 641
8.5 Universal Asynchronous Receivers/Transmitters (UARTs) 642
8.5.1 Asynchronous Serial Communication Protocols and Data Framing 642
8.5.2 Asynchronous Serial Interface Architecture and Functional Block Diagram 643
8.5.3 UART Module Operations and Control Registers 645
8.5.4 UART Module Control Signals and Related GPIO Pins 658
8.5.5 UART Module Initializations and Configurations 659
8.5.6 Build an Example UART Module Project 660
8.5.7 The UART API Functions Provided by the TivaWareTM Peripheral Driver Library 664
8.6 Chapter Summary 668
Homework 669
Chapter 9 ARM® Cortex®-M4 Timer and USB Programming 691
9.1 Overview and Introduction 691
9.2 General-Purpose Timers 692
9.2.1 The GPTM Architecture and Functional Block Diagram 693
9.2.2 The General-Purpose Timer Module Components 694
9.2.3 The General-Purpose Timer Module Operational Modes 695
9.2.4 The General-Purpose Timer Module Registers 704
9.2.5 The General-Purpose Timer Module GPIO-Related Control Signals 712
9.2.6 The General-Purpose Timer Module Initializations and Configurations 713
9.2.7 Build an Example General Purpose Timer Project 717
9.2.8 Popular Implementations on GPTM Modules 718
9.2.9 The API Functions Used for General-Purpose Timer Module 727
9.3 Watchdog Timers 732
9.3.1 The Watchdog Timer Architecture and Functional Block Diagram 734
9.3.2 The Watchdog Timer Operational Sequence and Timing Access 735
9.3.3 The Watchdog Timer Registers 735
9.3.4 The Watchdog Timer Module Initializations and Configurations 738
9.3.5 Build an Example Watchdog Timer Project 739
9.3.6 The API Functions Used for Watchdog Timer Modules 739
9.4 Universal Serial Bus (USB) Controller 743
9.4.1 The Hardware Configuration of the USB Devices 744
9.4.2 The USB Components and Operational Sequence 745
9.4.3 The Serial Interface Protocol of the USB Communications 747
9.4.4 The USB Interface Used in the Embedded System 748
9.4.5 The USB in the TM4C123GH6PM MCU System 749
9.4.6 The USB Registers 761
9.4.7 The USB Initializations and Configurations 774
9.4.8 A USB Implementation Example Project 775
9.4.9 The USB API Functions Provided by the TivaWareTM Peripheral Driver Library 780
9.4.10 Build a USB Implementation Example Project Using the API Functions 788
9.5 Chapter Summary 788
Homework 790
Chapter 10 ARM® Cortex®-M4 Other Peripherals Programming 805
10.1 Overview and Introduction 805
10.2 The Controller Area Network (CAN) 805
10.2.1 CAN Standard Frame 806
10.2.2 CAN Extended Frame 807
10.2.3 Detecting and Signaling Errors 808
10.2.4 The CAN Functional Block Diagram in the TM4C123GH6PM System 809
10.2.5 The CAN Components and Operational Procedures 810
10.2.6 The CAN Module Registers 823
10.2.7 The CAN Module Interfacing and External Control Signals 833
10.2.8 The CAN API Functions Provided by TivaWareTM Peripheral Driver Library 834
10.2.9 A CAN Module Implementation Example Project 838
10.3 The Quadrature Encoder Interface (QEI) 847
10.3.1 Introduction to Quadrature Encoder 847
10.3.2 The Working Principle of the Increment Rotary Encoder 849
10.3.3 The Increment Rotary Encoder Applied in the Closed-Loop Control System 850
10.3.4 The Increment Rotary Encoder Applied in the TM4C123GH6PM MCU System 851
10.3.5 The QEI Module Registers 852
10.3.6 The QEI Interfacing Signals and Related GPIO Pins 856
10.3.7 The QEI Initialization and Configuration Process 856
10.3.8 QEI API Functions Provided by the TivaWareTM Peripheral Driver Library 857
10.3.9 An Implementation of Using Rotary Encoder for a Closed-Loop Control System 860
10.4 The Continuous and Discrete PID Closed-Loop Control System 871
10.4.1 Identify the Dynamic Model for the Motor Plant 873
10.4.2 Design the PID Controller Using the MATLAB®Control System ToolboxTM 878
10.4.3 Simulate the PID Control System Using the MATLAB® SIMULINK® 881
10.4.4 Build the Control Software to Implement the PID Controller 883
10.5 The Fuzzy Logic Closed-Loop Control System 887
10.5.1 The Fuzzification Process 887
10.5.2 Design of Control Rules 889
10.5.3 The Defuzzification Process 889
10.5.4 Apply the Fuzzy Logic Controller to the DC Motor Control System 891
10.5.5 Build the Fuzzy Logic Control Project Fuzzy-Control 894
10.6 The Analog Comparators 899
10.6.1 The Analog Comparator Architecture and Functional Block Diagram 899
10.6.2 The Control Registers Used in the Analog Comparator Modules 899
10.6.3 The Voltage Reference Registers Used in the Analog Comparator Modules 900
10.6.4 The Interrupt Processing Registers Used in the Analog Comparator Modules 903
10.6.5 The Input and Output Control Signals Used in the Analog Comparators 903
10.6.6 The Initialization and Configuration Process for the Analog Comparator 904
10.6.7 Build a Project to Test the Functions of the Analog Comparator Module 904
10.6.8 Set Up the Environments to Build and Run the Project 907
10.7 Chapter Summary 908
Homework 909
Chapter 11 ARM® Floating Point Unit (FPU) 927
11.1 Overview and Introduction 927
11.2 Three Types of the Floating-Point Data 928
11.2.1 The Half-Precision Floating-Point Data 928
11.2.2 The Single-Precision Floating-Point Data 930
11.2.3 The Double-Precision Floating-Point Data 932
11.3 The FPU in the Cortex®-M4 MCU 934
11.3.1 The Architecture of the Floating-Point Registers 934
11.3.2 The FPU Operational Modes 937
11.4 Implementing the Floating-Point Unit 938
11.4.1 Floating-Point Support in CMSIS-Core 938
11.4.2 Floating-Point Programming in the TM4C123GH6PM MCU System 939
11.4.3 An FPU Example Project Using the Direct Register Access Model 942
11.5 Chapter Summary 946
Homework 946
Chapter 12 ARM® Memory Protection Unit (MPU) 951
12.1 Overview and Introduction 951
12.2 Implementation of the MPU 952
12.2.1 Memory Regions, Types, and Attributes 953
12.2.2 MPU Configuration and Control Registers 953
12.3 Initialization and Configuration of the MPU 959
12.4 Building A Practical Example MPU Project 960
12.4.1 Create a New DRA Model MPU Project DRAMPU 960
12.4.2 Set Up the Environment to Build and Run the Project 963
12.5 The API Functions Provided by the TivaWareTM Peripheral Driver Library 964
12.5.1 The MPU Set Up and Status API Functions 965
12.5.2 The MPU Enable and Disable API Functions 967
12.5.3 The MPU Interrupt Handler Control API Functions 968
12.6 Chapter Summary 969
Homework 970
Index 975
About the Author 987
Copyright Permissions
All copyright permitted Figures and Tables used in this book are listed below based on the different venders and companies.
Table I lists the copyright permitted Figures and Tables originated by the Texas Instruments Incorporated and used in this book. All those Figures and Tables have been permitted to be re-printed in this book under the copyright permissions of the Texas Instruments Incorporated.
Table I Copyright Permitted Figures and Tables by Texas Instruments Incorporated.
Chapter Figures and Tables Page Chapter 2 Figure 2.14: Block diagram of TM4C123GH6PM MCU.Figure 2.17: Function block diagram of Analog/Digital GPIO control.
Figure 2.20: The TM4C123GXL evaluation board.
Figure 2.21: The functional block diagram of the LaunchPad board.
Table 2.3: Exception and interrupt types and priority numbers.
Table 2.8: GPIO Pins with special considerations. 39
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58 Chapter 4 Figure 4.34: An example of using mask byte to do data reading and writing. 230 Chapter 5 Figure 5.6: An example of the NVIC Priority Level Register PRI0. 276 Chapter 6 Figure 6.3: Bit field and function on BOOTCFG Register.
Figure 6.4: Bit field and function on FMA Register.
Figure 6.5: Bit field and function on the FMC Register.
Figure 6.6: Bit field and function on the FMC2 Register.
Figure 6.7: Bit field and function on FCRIS Register.
Figure 6.8: Bit field and function on FCIM Register.
Figure 6.9: Bit field and function on FCMISC Register.
Figure 6.11: The functional block diagram of the EEPROM.
Figure 6.12: The bit field values and related functions in the EEDONE register.
Figure 6.13: The bit field values and related functions in the EEPROT register. 339
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360 Chapter 7 Figure 7.12: The bit fields for the ADCSSMUX0 register.
Figure 7.13: The bit fields for the ADCSSMUX1, 2 registers.
Figure 7.14: The bit fields for the ADCSSMUX3 register.
Figure 7.15: The bit fields for the ADCSSCTL0 register.
Figure 7.16: The bit fields for the ADCSSCTL1, 2 registers.
Figure 7.17: The bit fields for the ADCSSCTL3 register.
Figure 7.32: PWM Count-Down and Count Up/Down modes.
Figure 7.33: An example of using the count-up/down mode to generate PWM outputs.
Figure 7.34: The output PWM signals generated by Dead-Band generator.
Figure 7.35: The detailed block diagram for the PWM Generator block.
Figure 7.36: Bit fields in the PWM generator control register.
Figure 7.37: Bit fields in the PWM generator A register.
Figure 7.41: Architecture and functional block diagram of PWM module.
Figure 7.42: Bit fields in the Run-Mode Clock Configuration (RCC) register. 452
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Figure 8.4: Functional block diagram of the SSI module.
Figure 8.5: Operational timing sequence of the TI synchronous serial frame.
Figure 8.6: The operational sequence for Freescale SPI frame (SPO = SPH = 0).
Figure 8.7: The operational sequence for Freescale SPI frame (SPO = 0, SPH = 1).
Figure 8.8: The operational sequence for MACROWIRE frame.
Figure 8.11: The bit field and functions of the SSICR0 Register.
Figure 8.42: The I2C bus configuration and status.
Figure 8.43: The definition of START and STOP conditions.
Figure 8.44: The functional block diagram of each I2C module.
Figure 8.45: The I2C data transfer format and frame.
Figure 8.46: The operational sequence of the master working in the transmit mode.
Figure 8.47: The operational sequence of the master working in the receive mode.
Figure 8.48: The operational sequence of the I2C module working in the slave mode.
Figure 8.62: The functional block diagram for one UART module.
Figure 8.65: Bit configurations of the UARTCTL register. 556
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652 Chapter 9 Figure 9.1: The architecture and block diagram of one GPTM block.
Figure 9.3: An example of using a count-down timer to detect input edge events.
Figure 9.4: An example of using the count-down mode timer to detect the edge time.
Figure 9.5: An example of using Timer A to generate a PWM signal.
Figure 9.20: The functional block diagram of the watchdog modules.
Figure 9.27: Functional block diagram of the USB module. 693
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760 Chapter 10 Figure 10.2: A typical standard CAN frame format.
Figure 10.3: Functional block diagram of the CAN modules.
Figure 10.5: A normal CAN bit time configuration.
Figure 10.25: Functional block diagram of the QEI Modules.
Figure 10.26: The inversion and swapping logic circuit.
Figure 10.63: Architecture and functional block diagram of the Analog Comparator modules. 807
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Table II lists the copyright permitted Figures and Tables originated by the ARM Limited and used in this book. All those Figures and Tables have been reproduced with permission from ARM Limited. Copyright © ARM Limited.
Table II Copyright Permitted Figures and Tables by ARM Limited.
Chapter Figures and Tables Page Chapter 3 Figure 3.4: The components included in the MDK Core.Figure 3.5: Components in the Software Packs.
Figure 3.9: The opened Keil® MDK-ARM µVersion® 5.1 suite.
Figure 3.11: The opened Hello World project.
Figure 3.12: The opened source file hello.c.
Figure 3.13: Rebuild the hello project.
Figure 3.14: The building result of the hello project.
Figure 3.15: The debugging result of the hello world project.
Figure 3.16: The opened MDK-ARM IDE.
Figure 3.17: The opened Device Database wizard.
Figure 3.18: The detailed information for the device TM4C123GH6PM.
Figure 3.19: The License Management wizard.
Figure 3.20: An example of the Configuration submenu.
Figure 3.22: The Select Device for Target wizard.
Figure 3.23: The Manage Run-Time Environment wizard.
Figure 3.24: The selected components in the Manage Run-Time Environment wizard.
Figure 3.25: The new project wizard.
Figure 3.26: The Add New Item to Group wizard.
Figure 3.28: The finished codes for the source file MyProject.c.
Figure 3.29: Add a header file MyProject.h into the project.
Figure 3.31: The finished header file MyProject.h.
Figure 3.32: The project building process.
Figure 3.33: The finished debugger checking wizard.
Figure 3.34: The download process for our project.
Figure 3.35: The debug process for our project.
Figure 3.36: The Components, Environment, Books wizard.
Figure 3.37: The Manage Run-Time Environment wizard for our sample project.
Figure 3.38: Functions provided by the Options for Target Project wizard.
Figure 3.39: The Target option for the sample project MyProject.
Figure 3.40: The Output option for the sample project MyProject.
Figure 3.41: The Listing option for the sample project MyProject.
Figure 3.42: The Debug option for the sample project MyProject.
Figure 3.43: The Utilities option for the sample project MyProject.
Figure 3.44: The opened Settings wizard.
Figure 3.45: An example of using System Viewer for TIMER0 device.
Figure 3.46: The Nested Vectored Interrupt Controller configuration dialog.
Figure 3.50: A debug example for our sample project MyProject.
Figure 3.51: The optimization wizard for our sample project.
Figure 3.52: An example of using the code optimization under the Target tab. 87
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141 Chapter 4 Figure 4.38: The finished Options wizard. 236 Chapter 6 Figure 6.26: The running result of the project DRAFlash.
Figure 6.27: The 1-KB erased flash memory block (0x1000~0x13FF).
Figure 6.32: The running result of the DRAFlashInt...
