Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
1st Edition
Published on 22. October 2011
XXII, 170 pages
978-1-4614-0872-7 (ISBN)
Description
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
More details
Series
Language
English
Place of publication
New York
United States
Publishing group
Springer US
Target group
Professional and scholarly
Product notice
Reflowable
Illustrations
XXII, 170 p.
File size
4,24 MB
ISBN-13
978-1-4614-0872-7 (9781461408727)
DOI
10.1007/978-1-4614-0872-7
Schweitzer Classification
Other editions
Additional editions
Sumit Ahuja | Avinash Lakshminarayana | Sandeep Kumar Shukla
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Book
10/2014
Springer
€106.99
Shipment within 15-20 days
Sumit Ahuja | Avinash Lakshminarayana | Sandeep Kumar Shukla
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Book
10/2011
Springer
€106.99
Shipment within 15-20 days
Content
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.
